dds: improve comment

src/dds.rs

@@ -187,6 +187,9 @@ where
     }
 
     // Change external clock source (ref_clk)
+    // This will always provide a legitimate f_sys_clk by the following priority
+    // 1. Keep DDS clock tree untouched, record the new f_sys_clk
+    // 2. Use the default divided-by-2 clock tree, if PLL configuration becomes invalid
     pub fn set_ref_clk_frequency(&mut self, f_ref_clk: f64) -> Result<(), Error<E>> {
         // Override old reference clock frequency (ref_clk)
         self.f_ref_clk = f_ref_clk;