forked from M-Labs/humpback-dds
migen: take nmigen place
This commit is contained in:
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37d960669a
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3793d6d67c
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@ -0,0 +1,34 @@
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from humpback import HumpbackPlatform
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from migen.fhdl.module import Module
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class UrukulConnector(Module):
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def __init__(self, platform):
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# Request EEM I/O & SPI
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eem = platform.request("eem", 1)
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spi = platform.request("spi")
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# Assert signal length
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assert len(eem.p) == 8
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assert len(eem.n) == 8
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assert len(spi.sclk) == 1
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assert len(spi.mosi) == 1
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assert len(spi.miso) == 1
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assert len(spi.cs) == 3
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# Flip positive signal as negative output
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self.comb += eem.n.eq(~eem.p)
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# Link EEM to SPI
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self.comb += [
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eem.p[0].eq(spi.sclk),
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eem.p[1].eq(spi.mosi),
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eem.p[2].eq(spi.miso),
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eem.p[3].eq(spi.cs[0]),
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eem.p[4].eq(spi.cs[1]),
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eem.p[5].eq(spi.cs[2]),
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]
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if __name__ == "__main__":
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platform = HumpbackPlatform()
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platform.build(UrukulConnector(platform))
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@ -0,0 +1,42 @@
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# Import built in I/O, Connectors & Platform template
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from migen.build.platforms.sinara.humpback import _io, _connectors, Platform
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# Import migen platform for Lattice Products
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from migen.build.lattice import LatticePlatform
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# Import migen pin record structure
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from migen.build.generic_platform import *
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# Modify the SPI record, to include all 3 CS pins
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'''
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sclk -> PA5 : C8
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mosi -> PB5 : N5
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miso -> PA6 : T2
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cs_0 -> PB12: B13
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cs_1 -> PA15: B14
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cs_2 -> PC7 : B15
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'''
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# Filter out SPI record
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_io = [record for record in _io if record[0] != "spi"]
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# Reinsert new SPI record
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_io.append(
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("spi", 0,
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Subsignal("cs" , Pins("B13 B14 B15")),
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Subsignal("sclk", Pins("C8")),
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Subsignal("mosi", Pins("N5")),
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Subsignal("miso", Pins("T2")),
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IOStandard("LVCMOS33"),
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)
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)
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# Inherit Platform to gain the programmed clock attribute
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class HumpbackPlatform(Platform):
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def __init__(self):
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LatticePlatform.__init__(self, "ice40-hx8k-ct256", _io, _connectors, toolchain="icestorm")
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# Syntax check for direct execution
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if __name__ == "__main__":
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platform = HumpbackPlatform()
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@ -0,0 +1,22 @@
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{ stdenv, fetchFromGitHub, python3Packages }:
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python3Packages.buildPythonPackage rec {
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name = "migen";
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src = fetchFromGitHub {
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owner = "m-labs";
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repo = "migen";
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rev = "7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa";
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sha256 = "039jk8y7f0vhr32svg3nd23i88c0bhws8ngxwk9bdznfxvhiy1h6";
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fetchSubmodules = true;
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};
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propagatedBuildInputs = with python3Packages; [ colorama ];
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meta = with stdenv.lib; {
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description = "A refreshed Python toolbox for building complex digital hardware";
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homepage = "https://m-labs.hk";
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license = licenses.bsd2;
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maintainers = [ maintainers.sb0 ];
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};
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}
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@ -6,19 +6,38 @@ from nmigen import *
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from humpback import *
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from humpback import *
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class SimpleBlink(Elaboratable):
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#class SimpleBlinky(Elaboratable):
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def elaborate(self, platform):
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# def elaborate(self, platform):
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led = platform.request("user_led", 0)
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# led = platform.request("user_led", 0)
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counter = Signal(24)
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# counter = Signal(24)
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pin = platform.request("gpioa", 0)
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# m = Module()
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# m.d.sync += counter.eq(counter + 1)
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# m.d.comb += led.o.eq(counter[23])
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# return m
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# Simple connector from STM32 SPI to Humpback SPI
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class UrukulConnector(Elaboratable):
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def elaborate(self, platform):
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# Acquire SPI slave, EEM port 1 output
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spi = platform.request("spi")
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print(spi)
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eem = platform.request("eem", 1)
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print(eem)
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clk25 = platform.request("clk25")
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counter = Signal(25)
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m = Module()
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m.domains.sync = ClockDomain()
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m.d.comb += ClockSignal().eq(clk25.i)
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m.d.sync += counter.eq(counter + 1)
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return m
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m = Module()
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m.d.sync += counter.eq(counter + 1)
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m.d.comb += led.o.eq(counter[23])
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m.d.comb += pin.o.eq(led)
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return m
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if __name__ == "__main__":
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if __name__ == "__main__":
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platform = HumpbackPlatform()
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platform = HumpbackPlatform()
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platform.build(SimpleBlink(), do_program=False)
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platform.add_resources(platform.eem_to_urukul)
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platform.add_resources(platform.spi)
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platform.build(UrukulConnector(), do_program=False)
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@ -285,27 +285,49 @@ class HumpbackPlatform(LatticeICE40Platform):
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}),
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}),
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]
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]
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# Half completed, second EEM resource to be added
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# Half completed, second EEM resource to be added
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# Appears that DiffPairs cause build problem
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# eem_to_urukul_diffpairs = [
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# Resource("eem", 1,
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# Subsignal("sclk", DiffPairs("L6", "L3", dir="o")),
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# Subsignal("mosi", DiffPairs("H6", "F1", dir="o")),
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# Subsignal("miso", DiffPairs("H4", "G2", dir="i"),
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# Attrs(IO_STANDARD="SB_LVDS_INPUT")),
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# Subsignal("cs", DiffPairs("K1 J2 J4", "K3 J1 H2", dir="o")),
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# Subsignal("io_update", DiffPairs("L4", "L1", dir="o")),
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# Subsignal("sync_out", DiffPairs("K4", "M1", dir="o")),
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# Attrs(IO_STANDARD="SB_LVCMOS")
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# )
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# ]
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eem_to_urukul = [
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eem_to_urukul = [
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Resource("eem", 1,
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Resource("eem", 1,
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Subsignal("sclk", DiffPairs("L6", "L3", dir="o", conn=("eem", 1))),
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Subsignal("sclk_p", Pins("L6", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("mosi", DiffPairs("H6", "F1", dir="o", conn=("eem", 1))),
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Subsignal("sclk_n", Pins("L3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("miso", DiffPairs("H4", "G2", dir="i", conn=("eem", 1)),
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# Subsignal("sclk", DiffPairs("L6", "L3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Attrs(IO_STANDARD="SB_LVDS_INPUT")),
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Subsignal("mosi_p", Pins("H6", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("cs", DiffPairs("J4 J2 K1", "H2 J1 K3", dir="o", conn=("eem", 1))),
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Subsignal("mosi_n", Pins("F1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("io_update", DiffPairs("L4", "L1", dir="o", conn=("eem", 1))),
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# Subsignal("miso_p", Pins("H4", dir="i"), Attrs(IO_STANDARD="SB_IDK")),
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Subsignal("sync_out", DiffPairs("K4", "M1", dir="o", conn=("emm", 1))),
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# Subsignal("miso_n", Pins("G2", dir="i"), Attrs(IO_STANDARD="SB_LOL")),
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Attrs(IO_STANDARD="SB_LVCMOS")
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Subsignal("miso", DiffPairs("H4", "G2", dir="i"), Attrs(IO_STANDARD="SB_LVDS_INPUT")),
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)
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Subsignal("cs_p", Pins("J4 J2 K1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("cs_n", Pins("H2 J1 K3", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("io_update_p", Pins("L4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("io_update_n", Pins("L1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("sync_out_p", Pins("K4", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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Subsignal("sync_out_n", Pins("M1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
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),
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]
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]
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# SPI Connection
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# SPI Connection to Urukul, using (PD14, PA15, PC7) as connection pins
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spi = [
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spi = [
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Resource("spi", 0,
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Resource("spi", 0,
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Subsignal("cs", PinsN("R2", dir="i", conn=("stm32", 0))),
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Subsignal("cs", Pins("R2 B14 B15", dir="i")),
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Subsignal("mosi", Pins("N5", dir="i", conn=("stm32", 0))),
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Subsignal("mosi", Pins("N5", dir="i")),
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Subsignal("miso", Pins("T2", dir="oe", conn=("stm32", 0))),
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Subsignal("miso", Pins("T2", dir="oe")),
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Subsignal("sck", Pins("C8", dir="i", conn=("stn32", 0))),
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Subsignal("sck", Pins("C8", dir="i"),
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Attrs(GLOBAL=True)),
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Attrs(IO_STANDARD="SB_LVCMOS")
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Attrs(IO_STANDARD="SB_LVCMOS")
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)
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)
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]
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]
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iceprog = os.environ.get("ICEPROG", "iceprog")
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iceprog = os.environ.get("ICEPROG", "iceprog")
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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with products.extract("{}.bin".format(name)) as bitstream_filename:
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subprocess.check_call([iceprog, "-S", bitstream_filename])
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subprocess.check_call([iceprog, "-S", bitstream_filename])
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if __name__ == "__main__":
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from nmigen_boards.test.blinky import *
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platform = HumpbackPlatform()
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platform.add_resources(platform.eem_to_urukul)
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platform.add_resources(platform.spi)
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platform.build(Blinky(), do_program=False)
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@ -1,7 +1,7 @@
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from nmigen.build import *
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from nmigen.build import *
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__all__ = ["I2CResource", "GPIOResources", "DiffResources"]
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__all__ = ["I2CResource"]
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def I2CResource(*args, sda, scl, conn=None, attrs=None, role="host"):
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def I2CResource(*args, sda, scl, conn=None, attrs=None, role="host"):
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@ -22,6 +22,7 @@ def I2CResource(*args, sda, scl, conn=None, attrs=None, role="host"):
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io.append(attrs)
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io.append(attrs)
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return Resource.family(*args, default_name="i2c", ios=io)
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return Resource.family(*args, default_name="i2c", ios=io)
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'''
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# Auto create a resource list given a set of iCE40 pins and STM32 pin names (pins_dict)
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# Auto create a resource list given a set of iCE40 pins and STM32 pin names (pins_dict)
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def GPIOResources(*args, pins_dict, dir = "o", invert=False, conn=None, attrs=None):
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def GPIOResources(*args, pins_dict, dir = "o", invert=False, conn=None, attrs=None):
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@ -79,8 +80,7 @@ if __name__ == "__main__":
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DiffResources(eem_pins = eem, dir = "o",
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DiffResources(eem_pins = eem, dir = "o",
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attrs=Attrs(IO_STANDARD="SB_LVCMOS")
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attrs=Attrs(IO_STANDARD="SB_LVCMOS")
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)
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)
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'''
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14
shell.nix
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shell.nix
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@ -3,11 +3,13 @@ let
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pkgs = import <nixpkgs> {overlays = [mozillaOverlay];};
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pkgs = import <nixpkgs> {overlays = [mozillaOverlay];};
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in with pkgs;
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in with pkgs;
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let
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let
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nmigen = callPackage ./nix/nmigen.nix {};
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migen = callPackage ./nix/migen.nix {};
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nmigen-boards = callPackage ./nix/nmigen-boards.nix { inherit nmigen; };
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# nMigen support for DiffPairs and IO_STANDARD="SB_LVDS_INPUT" seems questionable
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openocd = callPackage ./nix/openocd.nix {};
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nmigen = callPackage ./nix/nmigen.nix {};
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rustPlatform = callPackage ./nix/rustPlatform.nix {};
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nmigen-boards = callPackage ./nix/nmigen-boards.nix { inherit nmigen; };
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itm = callPackage ./nix/itm.nix {inherit rustPlatform;};
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openocd = callPackage ./nix/openocd.nix {};
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rustPlatform = callPackage ./nix/rustPlatform.nix {};
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itm = callPackage ./nix/itm.nix {inherit rustPlatform;};
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runOpenOcd = writeShellScriptBin "run-openocd" ''
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runOpenOcd = writeShellScriptBin "run-openocd" ''
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openocd \
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openocd \
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@ -70,7 +72,7 @@ in
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stdenv.mkDerivation {
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stdenv.mkDerivation {
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name = "nix-shell";
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name = "nix-shell";
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buildInputs = with rustPlatform.rust; [
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buildInputs = with rustPlatform.rust; [
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(pkgs.python3.withPackages(ps: [nmigen nmigen-boards]))
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(pkgs.python3.withPackages(ps: [ migen nmigen nmigen-boards]))
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pkgs.yosys
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pkgs.yosys
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pkgs.nextpnr
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pkgs.nextpnr
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pkgs.icestorm
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pkgs.icestorm
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