forked from M-Labs/humpback-dds
attenuator: fix reverse data
This commit is contained in:
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29abca72cd
commit
181ef5c72a
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@ -1,5 +1,5 @@
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[target.thumbv7em-none-eabihf]
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runner = "gdb -q -x gdb_config/debug.gdb"
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runner = "gdb -q -x gdb_config/openocd.gdb"
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rustflags = [
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"-C", "link-arg=-Tlink.x",
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]
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@ -17,11 +17,16 @@ where
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pub fn new(spi: SPI) -> Self {
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Attenuator {
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spi,
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// data[y] refers to the yth byte for SPI communication
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data: [0, 0, 0, 0],
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}
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}
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pub fn set_attenuation(&mut self, att: [f32; 4]) -> Result<[u8; 4], Error<E>> {
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/*
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* Set attenuations of all attenuators
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* att[x] refers to the attenuation for channel x
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*/
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pub fn set_attenuation(&mut self, att: [f32; 4]) -> Result<(), Error<E>> {
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for i in 0..4 {
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let mut atten = att[i];
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if att[i] > 31.5 {
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@ -30,48 +35,49 @@ where
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if att[i] < 0.0 {
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atten = 0.0;
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}
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self.data[i] = (atten * 2.0) as u8;
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self.data[i] = self.data[i] << 2;
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// Set data as attenuation * 2
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// Flip data using bitwise XOR, active low data
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// Data is most signifant attenuator first
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self.data[3-i] = (((atten * 2.0) as u8) ^ 0xFF) << 2
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}
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let mut clone = self.data.clone();
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// Transmit SPI once to set attenuation
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if self.spi.transfer(&mut clone).map_err(Error::SPI).is_err() {
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return Err(Error::AttenuatorError);
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}
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// Transmit the same data again, to get the return value
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// Report the data returned by SPI, or an error
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clone = self.data.clone();
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match self.spi.transfer(&mut clone).map_err(Error::SPI) {
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Ok(arr) => {
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Ok([arr[0], arr[1], arr[2], arr[3]])
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},
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err => Err(Error::AttenuatorError)
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Err(e) => Err(Error::AttenuatorError),
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Ok(_) => Ok(()),
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}
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}
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pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<u8, Error<E>> {
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pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
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assert!(channel < 4);
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let mut arr: [f32; 4] = self.get_attenuation();
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let mut arr: [f32; 4] = self.get_attenuation()?;
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arr[channel as usize] = attenuation;
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match self.set_attenuation(arr) {
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Ok(v) => Ok(v[channel as usize]),
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Ok(v) => Ok(()),
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Err(e) => Err(e)
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}
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}
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pub fn get_channel_attenuation(&mut self, channel: u8) -> f32 {
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pub fn get_channel_attenuation(&mut self, channel: u8) -> Result<f32, Error<E>> {
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assert!(channel < 4);
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(self.data[channel as usize] as f32)/8.0
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match self.get_attenuation() {
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Ok(arr) => Ok(arr[channel as usize]),
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Err(e) => Err(e),
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}
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}
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pub fn get_attenuation(&mut self) -> [f32; 4] {
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[
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self.get_channel_attenuation(0),
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self.get_channel_attenuation(1),
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self.get_channel_attenuation(2),
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self.get_channel_attenuation(3),
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]
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pub fn get_attenuation(&mut self) -> Result<[f32; 4], Error<E>> {
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let mut clone = self.data.clone();
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match self.spi.transfer(&mut clone).map_err(Error::SPI) {
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Ok(arr) => {
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let mut ret :[f32; 4] = [0.0; 4];
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for index in 0..4 {
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ret[index] = ((arr[3 - index] ^ 0xFC) as f32) / 8.0;
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}
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Ok(ret)
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},
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Err(e) => Err(e),
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}
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}
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}
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124
src/main.rs
124
src/main.rs
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@ -84,8 +84,7 @@ fn main() -> ! {
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/*
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* I/O_Update -> PB13
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*/
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// TODO: Incoporate io_update into DDS
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let mut io_update = gpiob.pb15.into_push_pull_output();
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let io_update = gpiob.pb15.into_push_pull_output();
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let spi = dp.SPI1.spi(
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(sclk, miso, mosi),
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@ -94,7 +93,7 @@ fn main() -> ! {
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ccdr.peripheral.SPI1,
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&ccdr.clocks,
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);
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let mut switch = CPLD::new(spi, (cs0, cs1, cs2), io_update);
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let parts = switch.split();
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@ -119,18 +118,10 @@ fn main() -> ! {
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0x00, 0x00, 0x00, 0x02
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]).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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dds0.write_register(0x02, &mut[
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0x01F, 0x3F, 0xC0, 0x00
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0x01F, 0x3F, 0x41, 0x00
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]).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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hprintln!("{:#X?}", dds0.read_register(0x00, &mut[
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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@ -148,109 +139,36 @@ fn main() -> ! {
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dds0.read_register(0x0E, &mut profile).unwrap();
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// Overwrite FTW on profile
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profile[0] = 0x20;
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profile[4] = ((ftw >> 24) & 0xFF) as u8;
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profile[5] = ((ftw >> 16) & 0xFF) as u8;
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profile[6] = ((ftw >> 8 ) & 0xFF) as u8;
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profile[7] = ((ftw >> 0 ) & 0xFF) as u8;
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dds0.write_register(0x0E, &mut profile).unwrap();
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// io_update.set_high().unwrap();
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// io_update.set_low().unwrap();
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// switch.issue_io_update();
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hprintln!("{:#X?}", dds0.read_register(0x0E, &mut profile).unwrap()).unwrap();
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// Attenuator
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att.set_attenuation([
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0.0, 31.5, 24.0, 0.0
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]).unwrap();
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hprintln!("{:#X?}", att.get_attenuation().unwrap()).unwrap();
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/*
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cs0.set_low().unwrap();
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cs1.set_low().unwrap();
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cs2.set_low().unwrap();
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io_update.set_low().unwrap();
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let mut dummy :[u8;1] = [0];
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spi.transfer(&mut dummy);
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// Master reset DDS_0 through CPLD, with LED at 3
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x08, 0x00, 0x03
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]).unwrap();
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cs0.set_low().unwrap();
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// Perform I/O Reset through CPLD, with LED at 4
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x10, 0x00, 0x04
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]).unwrap();
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cs0.set_low().unwrap();
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// Release reset, control I/O Update through EEM
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// Relay clock signal from internal OSC (CLK_SEL = 0)
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// Enable Switch 0
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cs0.set_high().unwrap();
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spi.transfer(&mut [
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0x00, 0x00, 0x01
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]).unwrap();
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cs0.set_low().unwrap();
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cs0.set_low().unwrap();
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cs1.set_low().unwrap();
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cs2.set_high().unwrap();
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// Configure SDIO to be input only, enable 3-wires communication
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spi.transfer(&mut [
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0x00, 0x00, 0x00, 0x00, 0x02
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// Write to FTW register
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dds0.write_register(0x07, &mut [
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((ftw >> 24) & 0xFF) as u8,
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((ftw >> 16) & 0xFF) as u8,
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((ftw >> 8 ) & 0xFF) as u8,
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((ftw >> 0 ) & 0xFF) as u8,
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]).unwrap();
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// IO Update after every SPI transfer
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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// Bypass PLL, bypass divisor
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spi.transfer(&mut [
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0x02, 0x1F, 0x3F, 0xC0, 0x00
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]).unwrap();
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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hprintln!("{:#X?}", spi.transfer(&mut [
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0x82, 0x00, 0x00, 0x00, 0x00
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hprintln!("{:#X?}", dds0.read_register(0x07, &mut [
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0x00, 0x00, 0x00, 0x00
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]).unwrap()).unwrap();
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let f_out = 10_000_000.0;
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let f_sclk = 100_000_000.0;
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let resolution :u64 = 1 << 32;
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let ftw = ((resolution as f32) * f_out / f_sclk) as u32;
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hprintln!("{:#X}", ftw);
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// Read profile 0
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let mut profile_arr_0 :[u8; 9] = [0; 9];
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profile_arr_0[0] = 0x8E;
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hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap();
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// Write FTW to profile 0
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profile_arr_0[0] = 0x0E;
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profile_arr_0[5] = ((ftw >> 24) & 0xFF) as u8;
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profile_arr_0[6] = ((ftw >> 16) & 0xFF) as u8;
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profile_arr_0[7] = ((ftw >> 8 ) & 0xFF) as u8;
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profile_arr_0[8] = ((ftw >> 0 ) & 0xFF) as u8;
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hprintln!("{:#X?}", profile_arr_0).unwrap();
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spi.transfer(&mut profile_arr_0).unwrap();
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// Update after write
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io_update.set_high().unwrap();
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delay.delay_ms(1_u16);
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io_update.set_low().unwrap();
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// Read profile again, new value should be present
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profile_arr_0[0] = 0x8E;
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hprintln!("{:#X?}", spi.transfer(&mut profile_arr_0).unwrap()).unwrap();
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*/
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*/
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loop {}
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}
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