forked from M-Labs/humpback-dds
urukul: rebranded lib
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e17cc27cbb
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10d265b480
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extern crate embedded_hal;
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use embedded_hal::{
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blocking::spi::Transfer,
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};
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use crate::config_register::ConfigRegister;
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use crate::config_register::CFGMask;
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use crate::config_register::StatusMask;
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use crate::attenuator::Attenuator;
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use crate::dds::DDS;
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/*
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* Enum for structuring error
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*/
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#[derive(Debug)]
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pub enum Error<E> {
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SPI(E),
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CSError,
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GetRefMutDataError,
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AttenuatorError,
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IOUpdateError,
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DDSError,
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ConfigRegisterError,
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DDSCLKError,
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DDSRAMError,
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ParameterError,
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MqttTopicError,
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MqttCommandError,
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}
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#[derive(Debug, Clone)]
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pub enum ClockSource {
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OSC,
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SMA,
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MMCX,
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}
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/*
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* Struct for Urukul master device
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*/
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pub struct Urukul<SPI> {
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config_register: ConfigRegister<SPI>,
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attenuator: Attenuator<SPI>,
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multi_dds: DDS<SPI>,
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dds: [DDS<SPI>; 4],
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f_master_clk: f64,
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}
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impl<SPI, E> Urukul<SPI>
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where
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SPI: Transfer<u8, Error = E>,
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{
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/*
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* Master constructor for the entire Urukul device
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* Supply 7 SPI channels to Urukul and 4 reference clock frequencies
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*/
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pub fn new(spi1: SPI, spi2: SPI, spi3: SPI, spi4: SPI, spi5: SPI, spi6: SPI, spi7: SPI) -> Self {
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// Construct Urukul
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Urukul {
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config_register: ConfigRegister::new(spi1),
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attenuator: Attenuator::new(spi2),
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// Create a multi-channel DDS with predefined 25MHz clock
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multi_dds: DDS::new(spi3, 25_000_000.0),
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// Create 4 DDS instances with predefined 25MHz clock
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// Counter-intuitive to assign urukul clock before having a urukul
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dds: [
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DDS::new(spi4, 25_000_000.0),
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DDS::new(spi5, 25_000_000.0),
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DDS::new(spi6, 25_000_000.0),
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DDS::new(spi7, 25_000_000.0),
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],
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// Default clock selection: OSC, predefined 100MHz speed
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f_master_clk: 100_000_000.0,
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}
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}
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/*
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* Reset method. To be invoked by initialization and manual reset.
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* Only Urukul struct provides reset method.
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* DDS reset is controlled by Urukul (RST).
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* Attenuators only have shift register reset, which does not affect its data
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* CPLD only has a "all-zero" default state.
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*/
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pub fn reset(&mut self) -> Result<(), Error<E>> {
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// Reset DDS and attenuators
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self.config_register.set_configurations(&mut [
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(CFGMask::RST, 1),
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(CFGMask::IO_RST, 1),
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(CFGMask::IO_UPDATE, 0)
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])?;
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// Set 0 to all fields on configuration register.
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self.config_register.set_configurations(&mut [
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(CFGMask::RF_SW, 0),
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(CFGMask::LED, 0),
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(CFGMask::PROFILE, 0),
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(CFGMask::IO_UPDATE, 0),
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(CFGMask::MASK_NU, 0),
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::SYNC_SEL, 0),
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(CFGMask::RST, 0),
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(CFGMask::IO_RST, 0),
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(CFGMask::CLK_SEL1, 0),
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(CFGMask::DIV, 0),
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])?;
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// Init all DDS chips. Configure SDIO as input only.
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for chip_no in 0..4 {
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self.dds[chip_no].init()?;
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}
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// Clock tree reset. OSC clock source by default
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self.f_master_clk = 100_000_000.0;
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// CPLD divides clock frequency by 4 by default.
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for chip_no in 0..4 {
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self.dds[chip_no].set_ref_clk_frequency(self.f_master_clk / 4.0)?;
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}
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Ok(())
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}
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/*
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* Test method fo Urukul.
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* Return the number of test failed.
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*/
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pub fn test(&mut self) -> Result<u32, Error<E>> {
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let mut count = self.config_register.test()?;
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count += self.attenuator.test()?;
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for chip_no in 0..4 {
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count += self.dds[chip_no].test()?;
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}
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Ok(count)
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}
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}
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impl<SPI, E> Urukul<SPI>
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where
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SPI: Transfer<u8, Error = E>
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{
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pub fn get_channel_switch_status(&mut self, channel: u32) -> Result<bool, Error<E>> {
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if channel < 4 {
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self.config_register.get_status(StatusMask::RF_SW).map(|val| (val & (1 << channel)) != 0)
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} else {
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Err(Error::ParameterError)
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}
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}
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pub fn set_channel_switch(&mut self, channel: u32, status: bool) -> Result<(), Error<E>> {
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if channel < 4 {
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let prev = u32::from(self.config_register.get_status(StatusMask::RF_SW)?);
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let next = {
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if status {
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prev | (1 << channel)
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} else {
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prev & (!(1 << channel))
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}
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};
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self.config_register.set_configurations(&mut [
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(CFGMask::RF_SW, next),
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]).map(|_| ())
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} else {
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Err(Error::ParameterError)
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}
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}
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pub fn set_clock(&mut self, source: ClockSource, frequency: f64, division: u8) -> Result<(), Error<E>> {
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// Change clock source through configuration register
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self.set_clock_source(source)?;
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// Modify the master clock frequency
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// Prevent redundunt call to change f_ref_clk
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self.f_master_clk = frequency;
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self.set_clock_division(division)
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}
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pub fn set_clock_source(&mut self, source: ClockSource) -> Result<(), Error<E>> {
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// Change clock source through configuration register
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match source {
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ClockSource::OSC => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::CLK_SEL1, 0),
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]),
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ClockSource::MMCX => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 0),
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(CFGMask::CLK_SEL1, 1),
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]),
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ClockSource::SMA => self.config_register.set_configurations(&mut [
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(CFGMask::CLK_SEL0, 1),
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]),
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}.map(|_| ())
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}
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pub fn set_clock_frequency(&mut self, frequency: f64) -> Result<(), Error<E>> {
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// Update master clock frequency
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self.f_master_clk = frequency;
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// Update all DDS f_ref_clk
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self.set_dds_ref_clk()
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}
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pub fn set_clock_division(&mut self, division: u8) -> Result<(), Error<E>> {
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match division {
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1 => self.config_register.set_configurations(&mut [
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(CFGMask::DIV, 1),
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]),
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2 => self.config_register.set_configurations(&mut [
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(CFGMask::DIV, 2),
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]),
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4 => self.config_register.set_configurations(&mut [
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(CFGMask::DIV, 3),
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]),
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_ => Err(Error::ParameterError),
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}?;
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self.set_dds_ref_clk()
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}
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fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
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// Calculate reference clock frequency after clock division from configuration register
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let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
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// Update all DDS chips on reference clock frequency
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for dds_channel in 0..4 {
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self.dds[dds_channel].set_ref_clk_frequency(f_ref_clk)?;
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}
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Ok(())
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}
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fn get_master_clock_division(&mut self) -> u8 {
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match self.config_register.get_configuration(CFGMask::DIV) {
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0 | 3 => 4,
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1 => 1,
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2 => 2,
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_ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
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}
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}
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pub fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
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if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
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return Err(Error::ParameterError);
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}
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self.attenuator.set_channel_attenuation(channel, attenuation)
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}
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pub fn set_profile(&mut self, profile: u8) -> Result<(), Error<E>> {
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if profile >= 8 {
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return Err(Error::ParameterError);
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}
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self.config_register.set_configurations(&mut [
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(CFGMask::PROFILE, profile.into())
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]).map(|_| ())
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}
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pub fn set_channel_single_tone_profile(&mut self, channel: u8, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
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phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile(profile, frequency, phase, amplitude)
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}
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pub fn set_channel_single_tone_profile_frequency(&mut self, channel: u8, profile: u8, frequency: f64)-> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || frequency < 0.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile_frequency(profile, frequency)
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}
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pub fn set_channel_single_tone_profile_phase(&mut self, channel: u8, profile: u8, phase: f64)-> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || phase >= 360.0 || phase < 0.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile_phase(profile, phase)
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}
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pub fn set_channel_single_tone_profile_amplitude(&mut self, channel: u8, profile: u8, amplitude: f64)-> Result<(), Error<E>> {
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if channel >= 4 || profile >= 8 || amplitude < 0.0 || amplitude > 1.0 {
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return Err(Error::ParameterError);
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}
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self.dds[usize::from(channel)].set_single_tone_profile_amplitude(profile, amplitude)
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}
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pub fn set_channel_sys_clk(&mut self, channel: u8, f_sys_clk: f64) -> Result<(), Error<E>> {
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self.dds[usize::from(channel)].set_sys_clk_frequency(f_sys_clk).map(|_| ())
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}
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// Multi-dds channel functions
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// Do not allow reading of DDS registers
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// Make sure only 1 SPI transaction is compelted per function call
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// Setup NU_MASK in configuration register
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// This selects the DDS channels that will be covered by multi_channel DDS (spi3)
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// Note: If a channel is masked, io_update must be completed through configuration register (IO_UPDATE bit-field)
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// Implication: Deselect such channel if individual communication is needed.
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pub fn set_multi_channel_coverage(&mut self, channel: u8) -> Result<(), Error<E>> {
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self.config_register.set_configurations(&mut [
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(CFGMask::MASK_NU, channel.into())
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]).map(|_| ())
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}
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// Difference from individual single tone setup function:
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// - Remove the need of passing channel
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// All selected channels must share the same f_sys_clk
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pub fn set_multi_channel_single_tone_profile(&mut self, profile: u8, frequency: f64, phase: f64, amplitude: f64) -> Result<(), Error<E>> {
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if profile >= 8 || frequency < 0.0 || phase >= 360.0 ||
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phase < 0.0 || amplitude < 0.0 || amplitude > 1.0 {
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return Err(Error::ParameterError);
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}
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// Check f_sys_clk of all selected channels
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let selected_channels = self.config_register.get_configuration(CFGMask::MASK_NU);
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let mut found_a_selected_channel = false;
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let mut reported_f_sys_clk: f64 = 0.0;
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for channel_bit in 0..4 {
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if (selected_channels & (1 << (channel_bit as u8))) != 0 {
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if !found_a_selected_channel {
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found_a_selected_channel = true;
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reported_f_sys_clk = self.dds[channel_bit].get_f_sys_clk();
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} else if reported_f_sys_clk != self.dds[channel_bit].get_f_sys_clk() {
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return Err(Error::DDSError);
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}
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}
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}
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self.multi_dds.set_sys_clk_frequency(reported_f_sys_clk);
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self.multi_dds.set_single_tone_profile(profile, frequency, phase, amplitude)?;
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self.invoke_io_update()?;
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Ok(())
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}
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// Generate a pulse for io_update bit in configuration register
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// This acts like io_update in CPLD struct, but for multi-dds channel
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fn invoke_io_update(&mut self) -> Result<(), Error<E>> {
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self.config_register.set_configurations(&mut [
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(CFGMask::IO_UPDATE, 1)
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])?;
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self.config_register.set_configurations(&mut [
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(CFGMask::IO_UPDATE, 0)
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]).map(|_| ())
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}
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}
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