53 lines
1.3 KiB
Markdown
53 lines
1.3 KiB
Markdown
# WRPLL simulation
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A time domain simulation for WRPLL
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## Installing dependencies
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### Nix:
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```bash
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nix develop
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```
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### Others:
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```bash
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python -m venv .venv
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source .venv/bin/activate
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(venv) pip install -r requirements.txt
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```
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## Quick start
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- Three notebook examples are included
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1. `helper_PLL_example.ipynb` : helper PLL only
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2. `main_PLL_example.ipynb` : main PLL only with a user specific helper frequency
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3. `both_PLL_example.ipynb` : main and helper PLL
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- RAM usage and execution time estimate for simulation **ONLY**
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1. 100,000,000 time steps: 6GiB RAM and 12 seconds
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2. 200,000,000 time steps: 11GiB RAM and 20 seconds
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3. 300,000,000 time steps: 16GiB RAM and 35 seconds
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<br>
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<details><summary><b>WRPLL formulas</b></summary>
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- Assume the difference between $f_{main}, f_{gtx}$ is very small
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- Let $f_{in} = f_{main} = f_{gtx}$
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- $f_{helper} = f_{in} * \dfrac{N-1}{N}$
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- $f_{beat} = f_{in} - f_{helper} = \dfrac{f_{in}}{N}$
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- Main and helper Si549 DCXO **ADPLL** setting
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- $ADPLL = \dfrac{\Delta f_{outppm}}{0.0001164}$
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</details><br>
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## Limitation
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1. The simulation is missing the switching delay of "receiving ADPLL -> DCXO output starting to change"
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2. The white noise is used to simulate jitter which may result in higher phase noise
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