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wrpll-simulation
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docs: update limitation section

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morgan 2023-12-13 12:43:54 +08:00
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README.md
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@ -48,4 +48,5 @@ source .venv/bin/activate
</details><br>
## Limitation
As the simulation is not cycle nor delay accurate, there will be more glitches than the hardware implementation
1. The simulation is missing the switching delay of "receiving ADPLL -> DCXO output starting to change"
2. The white noise is used to simulate jitter which may result in higher phase noise