HDL guidelines

[edit] General guidelines

The code quality standard for inclusion of HDL modules is higher than what you may be used to.
Use Verilog HDL.
Use available FPGA resources sparingly and carefully. System-on-chip means you cannot take the whole FPGA for yourself.
Your design must meet timing.
Your design must work with Xst or another free of charge synthesizer. Most people cannot afford the licenses of Mentor Graphics, Synopsys, etc.
Your simulation must run with GPL Cver, Icarus Verilog or Verilator for the same reason. The free versions of Modelsim are tolerated as they are reasonably easy to obtain from FPGA vendors, but not recommended.
Keep everything synchronous. Reset signal is synchronous as well. If you really need to use multiple clock domains or another form of asynchronous logic, explain why.
Your design must come with a proper functional testbench.
LaTeX documentation is appreciated.
Use the same directory organization as elsewhere in the project. See http://github.com/lekernel/milkymist/tree/master/cores/hpdmc_ddr32/ for an example.
You must use a license compatible with GNU GPL.

Use "always @(*)" whenever possible.
Use Verilog-2001 port definitions, e.g. "module fnord(input foo, output bar);" instead of "module fnord(foo, bar); input foo; output bar;".
Always specify the bit lengths of the constants.
Use the same indentation schemes as in other places. Indentation character is a tabulation (width 8). See http://github.com/lekernel/milkymist/tree/master/cores/hpdmc_ddr32/rtl for examples.
No full_case or parallel_case directive. If your case statement is full or parallel, just make a full or parallel description.
Give explicit names to your ports, signals, and states.
Comment your code.