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ARTIQ (Advanced Real-Time Infrastructure for Quantum physics) is a next-generation control system for quantum information experiments. It is being developed in partnership with the Ion Storage Group at NIST, and its applicability reaches beyond ion trapping.

Modern research on quantum information systems poses particular challenges to the control system:

Enter ARTIQ

ARTIQ features a high-level programming language, based on Python, that helps describing complex experiments. It is compiled and executed on dedicated FPGA hardware with nanosecond timing resolution and sub-microsecond latency.

The time-critical code (a kernel) running on the FPGA (the core device) is easily interfaced with Python code on the computer using a remote procedure call (RPC) mechanism.

The FPGA design is highly portable so that it can adapt to different laboratory setups and resist hardware obsolescence.

ARTIQ drivers for non-realtime devices can be run on remote machines with different operating systems.

The project also includes a graphical user interface, an experiment scheduling system, and databases for experiments, devices, parameters and results.

Technologies employed include Python, Migen, MiSoC/mor1kx, LLVM and llvmlite.

Open source

Another goal of ARTIQ is to streamline and simplify the design flow of quantum physics instrumentation by promoting design reuse through the development of platform-independent, open-source hardware and software.

Our aim is to provide a control system suitable for the challenges of modern quantum information research, which is based on modular, parameterized and open components that allow physicists to rapidly design and deploy new experiments.

A taste of the programming language

Timing language basics

trigger.sync()               # wait for trigger input
start = now()                # capture trigger time
for i in range(3):
    delay(5*us)
    dds.pulse(900*MHz, 7*us) # first pulse 5 µs after trigger
at(start + 1*ms)             # re-reference time-line
dds.pulse(200*MHz, 11*us)    # exactly 1 ms after trigger

Parallelism

with sequential:
    with parallel:
        a.pulse(100*MHz, 10*us)
        b.pulse(200*MHz, 20*us)
    with parallel:
        c.pulse(300*MHz, 30*us)
        d.pulse(400*MHz, 20*us)

Organize experiment components and reuse code

class Experiment(AutoDB):
    def build(self):
        self.ion1 = Ion(...)
        self.ion2 = Ion(...)
        self.transporter = Transporter(...)

    @kernel
    def run(self):
        with parallel:
            self.ion1.cool(duration=10*us)
            self.ion2.cool(frequency=...)
        self.transporter.move(speed=...)
        delay(100*ms)
        self.ion1.detect(duration=...)

Is ARTIQ right for my lab?

It's easy to find out by yourself! The core device is based on the resource-efficient MiSoC system-on-chip design, and you can use a limited version of ARTIQ with the small and low-cost Papilio Pro board. Feel free to send feedback to the mailing list!

Note that ARTIQ is still in development and we expect to deploy a fully functional release (that will include a GUI) at NIST by June 2015.

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