LM32 documentation errata
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Contents |
[edit] Fields of the CFG CSR
| Document | LatticeMico32 Processor Reference Manual v8.0 |
|---|---|
| Page(s) | 12-13 |
| Description | Bit 3 should be the X field, and bit 4 should be the U field. The U field means that the CPU has user instructions (the documentation says it's "reserved"). "G" bit '1 = data cache is implemented'. This is incorrect -- the G big actually indicates whether debug is implemented. |
[edit] EID register
| Document | LatticeMico32 Processor Reference Manual v8.0 |
|---|---|
| Page(s) | 9, table 4 |
| Description | EID is described as the LM32 Revision Number. Later text describes this as the "Exception ID", which seems to fit better -- the LM32 Revision is accessible as part of the CFG CSR. |
[edit] Verilog configuration options
| Document | LatticeMico32 Processor Reference Manual v8.0 |
|---|---|
| Page(s) | 35, table 16 |
| Description | Configuration options have had the CFG_ prefix dropped with no note of this. Either prefix the config options with CFG_, or make a note to this effect in the text. Furthermore, DIVIDE_ENABLED is actually called MC_DIVIDE_ENABLED. |
[edit] Cache associativity
| Document | LatticeMico32 Processor Reference Manual v8.0 |
|---|---|
| Page(s) | 37, table 16 |
| Description | ICACHE_Associativity and DCACHE_Associativity do not explain clearly what is meant by "associativity" -- in this case, 1=Direct Mapped, 2=two-way set-associative. |
[edit] RAISE/SCALL instruction
| Document | LatticeMico32 Processor Reference Manual v8.0 |
|---|---|
| Page(s) | 50/77 |
| Description | RAISE instruction (p.50, opcode 101011) is listed in the Instruction Descriptions as "SCALL" (p. 77). There is no indication which of these names is correct. |
