add documentation links

artiq/sinara.page

@@ -14,16 +14,22 @@
 <h2>Kasli</h2>
 <p>One of the main devices in the Sinara family is the Kasli core device. It contains an Artix-7 100T FPGA, DDR3 SDRAM, three SFP connectors, and can control up to 8 daughtercards (Eurocard Extension Module, EEM). The Kasli and its EEMs are installed in one Eurocard 3U chassis. One SFP connector is used for a Gigabit Ethernet connection to your computer network.</p>
 
+<p><a href="https://github.com/sinara-hw/Kasli/wiki">More information</a></p>
+
 <p><center><img src="kasli.jpg" width="600"></center></p>
 
 <h2>TTL I/O EEMs</h2>
 <p>For simple TTL signals, we offer I/O cards with 8 channels over BNC or SMA connectors in the EEM form factor. The IOs are divided into two banks of 4, with per-bank ground isolation. The direction (input/output) and termination (high-Z/50R) is selectable on a per-channel basis via I2C or on-board switches. Outputs can supply 5V into 25Ohm, and can tolerate an indefinite short-circuit to ground.</p>
 
+<p>More information: <a href="https://github.com/sinara-hw/DIO_BNC/wiki">BNC card</a> <a href="https://github.com/sinara-hw/DIO_SMA/wiki">SMA card</a></p>
+
 <p><center><img src="dio_bnc.jpg" width="300"> <img src="dio_sma.jpg" width="300"></center></p>
 
 <h2>Urukul DDS card</h2>
 <p>Urukul is a 4 channel DDS-based frequency synthesizer for the EEM form factor. It provides sub-Hz frequency resolution, controlled phase steps, and accurate output amplitude control. We offer it in two variants, with either the AD9910 or the AD9912 chip.</p>
 
+<p><a href="https://github.com/sinara-hw/Urukul/wiki">More information</a></p>
+
 <p><center><img src="urukul.jpg" width="600"></center></p>
 
 <h2>Zotino DAC card</h2>
@@ -31,11 +37,15 @@
 
 <p>Zotino connects the 32 channels to both (a) a HD68 connector on its front panel and (b) to four IDC connectors on the board. Each IDC connection with 8 channels can be broken out to BNC using BNC-IDC.</p>
 
+<p><a href="https://github.com/sinara-hw/Zotino/wiki">More information</a></p>
+
 <p><center><img src="zotino.jpg" width="600"></center></p>
 
 <h2>Sampler ADC card</h2>
 <p>Sampler is an 8-channel, 16-bit ADC EEM with an update rate of up to 1.5MSPS (all channels simultaneously). It has low-noise differential front end with a digitally programmable gain, providing full-scale input ranges between +-10mV (G=1000) and +-10V (G=1).</p>
 
+<p><a href="https://github.com/sinara-hw/Sampler/wiki">More information</a></p>
+
 <p><center><img src="sampler.jpg" width="600"></center></p>
 
 <h2>Grabber camera interface</h2>
@@ -43,6 +53,8 @@
 
 <p>In the FPGA, frame data streamed through "ROI engines". Each ROI engine gates on one rectangular pixel region and accumulates pixel values for each frame. The ROI engines operate independently and can be overlapping. After the frame, the accumulated value is pushed as an RTIO input event. Regions of interest (ROI) can be configured at runtime, and are defined with the computer.</p>
 
+<p><a href="https://github.com/sinara-hw/Grabber/wiki">More information</a></p>
+
 <p><center><img src="grabber.jpg" width="350"></center></p>
 
 <h2>Purchasing Sinara hardware</h2>

migen/index.page

@@ -20,6 +20,10 @@ Documentation (note: sometimes out of date - please help!)<br />
 <li><a href="manual">User guide</a></li>
 <li><a href="tutorial.pdf">Tutorial: An introduction to Migen</a></li>
 <li><a href="slides.pdf">Lecture slides</a></li>
+<li><a href="https://www.wdj-consulting.com/blog/migen-port.html">Tutorial "Porting a New Board To Migen"</a> by cr1901</li>
+<li><a href="https://lab.whitequark.org/notes/2016-10-18/implementing-an-uart-in-verilog-and-migen/">"Implementing a UART in Verilog and Migen"</a> by whitequark</li>
+<li><a href="https://lab.whitequark.org/notes/2016-10-19/implementing-a-simple-soc-in-migen/">"Implementing a simple SoC in Migen"</a> by whitequark</li>
+<li><a href="http://blog.lambdaconcept.com/doku.php?id=migen:tutorial">Migen Step by Step Tutorial</a> by LambdaConcept</li>
 </ul>
 </p>