284 lines
7.5 KiB
Diff
284 lines
7.5 KiB
Diff
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diff --git a/boards/avnet-sp3aevl/rtl/system.v b/boards/avnet-sp3aevl/rtl/system.v
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index 33e7b26..178cfb1 100644
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--- a/boards/avnet-sp3aevl/rtl/system.v
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+++ b/boards/avnet-sp3aevl/rtl/system.v
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@@ -36,8 +36,7 @@ module system(
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// GPIO
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input [2:0] btn, // 3
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- output [3:0] led, // 2 (2 LEDs for UART activity)
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- input count
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+ output [3:0] led // 2 (2 LEDs for UART activity)
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);
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//------------------------------------------------------------------
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@@ -309,8 +308,7 @@ wire [13:0] csr_a;
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wire csr_we;
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wire [31:0] csr_dw;
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wire [31:0] csr_dr_uart,
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- csr_dr_sysctl,
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- csr_dr_counter;
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+ csr_dr_sysctl;
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//---------------------------------------------------------------------------
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// WISHBONE to CSR bridge
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@@ -334,7 +332,6 @@ csrbrg csrbrg(
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.csr_di(
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csr_dr_uart
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|csr_dr_sysctl
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- |csr_dr_counter
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)
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);
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@@ -519,30 +516,4 @@ sysctl #(
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.hard_reset(hard_reset)
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);
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-
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-//---------------------------------------------------------------------------
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-// Counter
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-//---------------------------------------------------------------------------
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-//wire [13:0] gpio_output
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-
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-counter #(
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- .csr_addr(4'h2)
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-) counter (
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- .sys_clk(sys_clk),
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- .sys_rst(sys_rst),
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-
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- //.gpio_irq(gpio_irq),
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- //.timer0_irq(timer0_irq),
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- //.timer1_irq(timer1_irq),
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-
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- .csr_a(csr_a),
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- .csr_we(csr_we),
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- .csr_di(csr_dw),
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- .csr_do(csr_dr_counter), //with CSR remenber add it there too
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-
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- .count_input(count) //count is fot the pin
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-
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-// .hard_reset(hard_reset)
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-);
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-
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endmodule
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diff --git a/boards/avnet-sp3aevl/sources.mak b/boards/avnet-sp3aevl/sources.mak
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index 47ea9e8..797628a 100644
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--- a/boards/avnet-sp3aevl/sources.mak
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+++ b/boards/avnet-sp3aevl/sources.mak
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@@ -22,6 +22,5 @@ NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash8/rtl/*.v)
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BRAM_SRC=$(wildcard $(CORES_DIR)/bram/rtl/*.v)
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UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
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SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
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-COUNTER_SRC=$(wildcard $(CORES_DIR)/counter/rtl/*.v)
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-CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC) $(COUNTER_SRC)
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+CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC)
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diff --git a/boards/avnet-sp3aevl/synthesis/common.ucf b/boards/avnet-sp3aevl/synthesis/common.ucf
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index 97fe532..60f9568 100644
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--- a/boards/avnet-sp3aevl/synthesis/common.ucf
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+++ b/boards/avnet-sp3aevl/synthesis/common.ucf
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@@ -61,9 +61,6 @@ NET "led(1)" LOC = C16 | IOSTANDARD = LVCMOS33;
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NET "led(2)" LOC = C15 | IOSTANDARD = LVCMOS33;
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NET "led(3)" LOC = B15 | IOSTANDARD = LVCMOS33;
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-# ==== Counter ====
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-NET "count" LOC = E13 | IOSTANDARD = LVCMOS33;
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-
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# ==== Prohibit Special Pins ====
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CONFIG PROHIBIT = T12; # FPGA_INIT_B
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CONFIG PROHIBIT = D5; # FPGA_PUDC
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diff --git a/cores/counter/doc/Makefile b/cores/counter/doc/Makefile
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deleted file mode 100644
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index 884d3c0..0000000
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--- a/cores/counter/doc/Makefile
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+++ /dev/null
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@@ -1,23 +0,0 @@
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-TEX=counter.tex
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-
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-DVI=$(TEX:.tex=.dvi)
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-PS=$(TEX:.tex=.ps)
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-PDF=$(TEX:.tex=.pdf)
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-AUX=$(TEX:.tex=.aux)
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-LOG=$(TEX:.tex=.log)
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-
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-all: $(PDF)
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-
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-%.dvi: %.tex
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- latex $<
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-
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-%.ps: %.dvi
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- dvips $<
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-
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-%.pdf: %.ps
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- ps2pdf $<
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-
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-clean:
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- rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
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-
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-.PHONY: clean
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diff --git a/cores/counter/doc/counter.tex b/cores/counter/doc/counter.tex
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deleted file mode 100644
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index 3b8a917..0000000
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--- a/cores/counter/doc/counter.tex
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+++ /dev/null
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@@ -1,46 +0,0 @@
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-\documentclass[a4paper,11pt]{article}
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-\usepackage{fullpage}
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-\usepackage[latin1]{inputenc}
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-\usepackage[T1]{fontenc}
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-\usepackage[normalem]{ulem}
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-\usepackage[english]{babel}
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-\usepackage{listings,babel}
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-\lstset{breaklines=true,basicstyle=\ttfamily}
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-\usepackage{graphicx}
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-\usepackage{moreverb}
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-\usepackage{url}
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-\usepackage{tabularx}
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-
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-\title{Simple Counter}
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-\author{Cristian Paul Penaranda Rojas}
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-\date{September 2010}
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-\begin{document}
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-\setlength{\parindent}{0pt}
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-\setlength{\parskip}{5pt}
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-\maketitle{}
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-\section{Overview}
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-
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-The counter have basic functionallity, is not intended for real applications yet, just educational porpuses:
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-
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-\section{Control}
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-
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-The counter can support maximum count of 32 bits also enable/disable by control registers.
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-
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-It is possible to generate an interrupt when the counter overflow.
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-
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-\begin{tabularx}{\textwidth}{|l|l|l|X|}
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-\hline
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-\bf{Offset} & \bf{Read/Write} & \bf{Default} & \bf{Description} \\
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-\hline
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-0x00 & W & 0 & Enable. \\
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-\hline
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-0x04 & R & N/A & Count. \\
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-\hline
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-\end{tabularx}\\
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-
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-
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-\section*{Copyright notice}
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-Copyright \copyright 2010 Cristian Paul Penaranda Rojas. \\
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-Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
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-
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-\end{document}
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diff --git a/cores/counter/rtl/count.v b/cores/counter/rtl/count.v
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deleted file mode 100644
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index ae3e43a..0000000
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--- a/cores/counter/rtl/count.v
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+++ /dev/null
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@@ -1,107 +0,0 @@
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-/*
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- * Milkymist VJ SoC
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- *
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- * Copyright (C) 2010 Cristian Paul Peñaranda Rojas
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- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
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- *
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- * This program is free software: you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation, version 3 of the License.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program. If not, see <http://www.gnu.org/licenses/>.
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- */
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-
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-module counter #(
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- parameter csr_addr = 4'h0
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-) (
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- input sys_clk,
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- input sys_rst,
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-
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- /* Interrupts & count */
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- //output reg count_irq,
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- output reg [31:0] counter0,
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- output reg [31:0] counter_c0,
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- output reg [31:0] counter_in0,
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-
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- /* CSR bus interface */
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- input [13:0] csr_a,
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- input csr_we,
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- input [31:0] csr_di,
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- output reg [31:0] csr_do,
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-
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- /* count clk input*/
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- input count_input
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-
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-);
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-
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-
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-
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-/* Synchronize the input */
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-reg count_in0;
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-reg count_in;
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-always @(posedge sys_clk) begin
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- count_in0 <= count_input;
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- count_in <= count_in0;
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-end
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-
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-/* Detect level changes and generate count */
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-reg count_inbefore;
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-always @(posedge sys_clk) count_inbefore <= count_in;
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-wire count_diff = count_inbefore ^ count_in;
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-reg count_irqen;
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-always @(posedge sys_clk) begin
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- if(sys_rst)
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- counter0 <= 32'd0;
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- else
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- counter0 <= counter0 + 1; //count
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-end
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-
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-/*
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- * Logic and CSR interface
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- */
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-
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-wire csr_selected = csr_a[13:10] == csr_addr;
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-//counter_0 = counter0;
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-//wire [31:0] counter_0 = {counter0};
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-wire [31:0] counter_0 = counter0;
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-//:counter0 = counter_c0;
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-
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-always @(posedge sys_clk) begin
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- if(sys_rst) begin
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- csr_do <= 32'd0;
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-
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-// counter_irq <= 1'b0;
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-
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- counter_c0 <= 32'd0;
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-
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- if(csr_selected) begin
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- /* CSR Writes */
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- if(csr_we) begin
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- case(csr_a[3:0])
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- /* control registers */
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- // 0000 enable
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- // 0001 counter soft reset
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- //4'b0000: en1 <= csr_di[0];
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- //4'b0001: counter_irqen <= csr_di[ninputs-1:0];
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- 4'b0000: counter_in0 <= csr_di[31:0]; //not used yet
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- endcase
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- end
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-
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- /* CSR Reads */
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- case(csr_a[3:0])
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- /* status registers */
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- /* 0100 count*/
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- 4'b0100: csr_do <= counter_0;
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- //pending irq when counter overflow
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- endcase
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- end
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- end
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-end
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-
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-endmodule
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