Sean Cross
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28ded4136a
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vexriscv: clone from riscv crate
Base the vexriscv crate on the riscv crate, but add vexriscv-specific
instructions.
Signed-off-by: Sean Cross <sean@xobs.io>
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2019-12-28 18:12:31 +08:00 |
Vadim Kaushan
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a659a0cc39
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Declare all the CSR registers in asm.S
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2019-06-25 23:33:40 +03:00 |
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Vadim Kaushan
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cf9008492a
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Add marchid, mhartid and mimpid registers
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2019-04-29 10:43:51 +02:00 |
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Vadim Kaushan
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5baba0cb32
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Add write function for sstatus register
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2019-03-28 18:56:49 +03:00 |
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Vadim Kaushan
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4fb81f4860
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Add FS and XS fields of mstatus
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2019-03-18 18:14:00 +03:00 |
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Vadim Kaushan
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4ad2150a24
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Add fcsr register
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2019-03-17 19:06:29 +03:00 |
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Vadim Kaushan
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a51143d366
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Implement asm functions
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2019-01-23 01:29:54 +03:00 |