M-Labs/vexriscv-rust
3
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove write functions for read-only registers

Browse Source
This commit is contained in:
Vadim Kaushan 2020-06-14 14:40:51 +03:00
parent 707f51f46e
commit e21ce5249f
No known key found for this signature in database
GPG Key ID: A501C5DF67C05C4E
4 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
asm.S
View File

@ -44,7 +44,7 @@ __clear_ ## name: \
// VexRiscv custom registers // VexRiscv custom registers
RW(0xBC0, vmim) // Machine IRQ Mask RW(0xBC0, vmim) // Machine IRQ Mask
RW(0xFC0, vmip) // Machine IRQ Pending RO(0xFC0, vmip) // Machine IRQ Pending
RW(0x9C0, vsim) // Supervisor IRQ Mask RW(0x9C0, vsim) // Supervisor IRQ Mask
RW(0xDC0, vsip) // Supervisor IRQ Pending RO(0xDC0, vsip) // Supervisor IRQ Pending
RW(0xCC0, vdci) // DCache Info RO(0xCC0, vdci) // DCache Info

1
src/register/vdci.rs
View File

@ -1,4 +1,3 @@
//! DCache Information register //! DCache Information register
read_csr_as_usize!(0xCC0, __read_vdci); read_csr_as_usize!(0xCC0, __read_vdci);
write_csr_as_usize!(0xCC0, __write_vdci);

1
src/register/vmip.rs
View File

@ -1,4 +1,3 @@
//! Machine IRQ Pending register //! Machine IRQ Pending register
read_csr_as_usize!(0xFC0, __read_vmip); read_csr_as_usize!(0xFC0, __read_vmip);
write_csr_as_usize!(0xFC0, __write_vmip);

1
src/register/vsip.rs
View File

@ -1,4 +1,3 @@
//! Supervisor IRQ Pending register //! Supervisor IRQ Pending register
read_csr_as_usize!(0xDC0, __read_vsip); read_csr_as_usize!(0xDC0, __read_vsip);
write_csr_as_usize!(0xDC0, __write_vsip);