Add marchid, mhartid and mimpid registers

asm.S

@@ -40,6 +40,9 @@ REG_READ_WRITE(mstatus, 0x300)
 REG_SET_CLEAR(mstatus, 0x300)
 REG_READ_WRITE(mtvec, 0x305)
 REG_READ(mvendorid, 0xF11)
+REG_READ(marchid, 0xF12)
+REG_READ(mimpid, 0xF13)
+REG_READ(mhartid, 0xF14)
 
 // S-mode registers
 REG_READ_WRITE(satp, 0x180)

src/register/marchid.rs

@@ -0,0 +1,27 @@
+//! marchid register
+
+use core::num::NonZeroUsize;
+
+/// marchid register
+#[derive(Clone, Copy, Debug)]
+pub struct Marchid {
+    bits: NonZeroUsize,
+}
+
+impl Marchid {
+    /// Returns the contents of the register as raw bits
+    pub fn bits(&self) -> usize {
+        self.bits.get()
+    }
+}
+
+read_csr!(0xF11, __read_marchid);
+
+/// Reads the CSR
+#[inline]
+pub fn read() -> Option<Marchid> {
+    let r = unsafe{ _read() };
+    // When marchid is hardwired to zero it means that the marchid
+    // csr isn't implemented.
+    NonZeroUsize::new(r).map(|bits| Marchid { bits })
+}

src/register/mhartid.rs

@@ -0,0 +1,3 @@
+//! mhartid register
+
+read_csr_as_usize!(0xf14, __read_mhartid);

src/register/mimpid.rs

@@ -0,0 +1,27 @@
+//! mimpid register
+
+use core::num::NonZeroUsize;
+
+/// mimpid register
+#[derive(Clone, Copy, Debug)]
+pub struct Mimpid {
+    bits: NonZeroUsize,
+}
+
+impl Mimpid {
+    /// Returns the contents of the register as raw bits
+    pub fn bits(&self) -> usize {
+        self.bits.get()
+    }
+}
+
+read_csr!(0xF11, __read_mimpid);
+
+/// Reads the CSR
+#[inline]
+pub fn read() -> Option<Mimpid> {
+    let r = unsafe{ _read() };
+    // When mimpid is hardwired to zero it means that the mimpid
+    // csr isn't implemented.
+    NonZeroUsize::new(r).map(|bits| Mimpid { bits })
+}

src/register/mod.rs

@@ -15,14 +15,17 @@ mod macros;
 
 pub mod fcsr;
 
+pub mod marchid;
 pub mod mcause;
 pub mod mcycle;
 pub mod mcycleh;
 pub mod mepc;
+pub mod mhartid;
 pub mod mie;
-pub mod mip;
+pub mod mimpid;
 pub mod minstret;
 pub mod minstreth;
+pub mod mip;
 pub mod misa;
 pub mod mstatus;
 pub mod mtvec;