From cf9008492a82acdb31541813c4ed5a24d2bf6a1b Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Mon, 29 Apr 2019 10:43:51 +0200
Subject: [PATCH] Add marchid, mhartid and mimpid registers

---
 asm.S                   |  3 +++
 src/register/marchid.rs | 27 +++++++++++++++++++++++++++
 src/register/mhartid.rs |  3 +++
 src/register/mimpid.rs  | 27 +++++++++++++++++++++++++++
 src/register/mod.rs     |  5 ++++-
 5 files changed, 64 insertions(+), 1 deletion(-)
 create mode 100644 src/register/marchid.rs
 create mode 100644 src/register/mhartid.rs
 create mode 100644 src/register/mimpid.rs

diff --git a/asm.S b/asm.S
index 1a83960..3f7202d 100644
--- a/asm.S
+++ b/asm.S
@@ -40,6 +40,9 @@ REG_READ_WRITE(mstatus, 0x300)
 REG_SET_CLEAR(mstatus, 0x300)
 REG_READ_WRITE(mtvec, 0x305)
 REG_READ(mvendorid, 0xF11)
+REG_READ(marchid, 0xF12)
+REG_READ(mimpid, 0xF13)
+REG_READ(mhartid, 0xF14)
 
 // S-mode registers
 REG_READ_WRITE(satp, 0x180)
diff --git a/src/register/marchid.rs b/src/register/marchid.rs
new file mode 100644
index 0000000..c10112e
--- /dev/null
+++ b/src/register/marchid.rs
@@ -0,0 +1,27 @@
+//! marchid register
+
+use core::num::NonZeroUsize;
+
+/// marchid register
+#[derive(Clone, Copy, Debug)]
+pub struct Marchid {
+    bits: NonZeroUsize,
+}
+
+impl Marchid {
+    /// Returns the contents of the register as raw bits
+    pub fn bits(&self) -> usize {
+        self.bits.get()
+    }
+}
+
+read_csr!(0xF11, __read_marchid);
+
+/// Reads the CSR
+#[inline]
+pub fn read() -> Option<Marchid> {
+    let r = unsafe{ _read() };
+    // When marchid is hardwired to zero it means that the marchid
+    // csr isn't implemented.
+    NonZeroUsize::new(r).map(|bits| Marchid { bits })
+}
diff --git a/src/register/mhartid.rs b/src/register/mhartid.rs
new file mode 100644
index 0000000..3960388
--- /dev/null
+++ b/src/register/mhartid.rs
@@ -0,0 +1,3 @@
+//! mhartid register
+
+read_csr_as_usize!(0xf14, __read_mhartid);
diff --git a/src/register/mimpid.rs b/src/register/mimpid.rs
new file mode 100644
index 0000000..e49a246
--- /dev/null
+++ b/src/register/mimpid.rs
@@ -0,0 +1,27 @@
+//! mimpid register
+
+use core::num::NonZeroUsize;
+
+/// mimpid register
+#[derive(Clone, Copy, Debug)]
+pub struct Mimpid {
+    bits: NonZeroUsize,
+}
+
+impl Mimpid {
+    /// Returns the contents of the register as raw bits
+    pub fn bits(&self) -> usize {
+        self.bits.get()
+    }
+}
+
+read_csr!(0xF11, __read_mimpid);
+
+/// Reads the CSR
+#[inline]
+pub fn read() -> Option<Mimpid> {
+    let r = unsafe{ _read() };
+    // When mimpid is hardwired to zero it means that the mimpid
+    // csr isn't implemented.
+    NonZeroUsize::new(r).map(|bits| Mimpid { bits })
+}
diff --git a/src/register/mod.rs b/src/register/mod.rs
index 0c38e38..d7219ec 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -15,14 +15,17 @@ mod macros;
 
 pub mod fcsr;
 
+pub mod marchid;
 pub mod mcause;
 pub mod mcycle;
 pub mod mcycleh;
 pub mod mepc;
+pub mod mhartid;
 pub mod mie;
-pub mod mip;
+pub mod mimpid;
 pub mod minstret;
 pub mod minstreth;
+pub mod mip;
 pub mod misa;
 pub mod mstatus;
 pub mod mtvec;