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@ -4,7 +4,7 @@ version = "0.3.0"
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repository = "https://github.com/rust-embedded/riscv"
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authors = ["David Craven <david@craven.ch>"]
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categories = ["embedded", "hardware-support", "no-std"]
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description = "Low level access to RISCV processors"
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description = "Low level access to RISC-V processors"
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keywords = ["riscv", "register", "peripheral"]
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license = "ISC"
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//! Low level access to RISCV processors
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//! Low level access to RISC-V processors
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//!
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//! This crate provides:
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//!
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//! RISCV CSR's
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//! RISC-V CSR's
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//!
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//! The following registers are not available on 64-bit implementations.
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//!
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