From ac1cba597ae3e98fb2e5e80ce370938bc3288c52 Mon Sep 17 00:00:00 2001
From: Vadim Kaushan <admin@disasm.info>
Date: Thu, 24 Jan 2019 17:19:32 +0300
Subject: [PATCH] Fix RISC-V name

https://riscv.org/risc-v-trademark-usage/
---
 Cargo.toml          | 2 +-
 src/lib.rs          | 2 +-
 src/register/mod.rs | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index 683f51a..7c29016 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -4,7 +4,7 @@ version = "0.3.0"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["David Craven <david@craven.ch>"]
 categories = ["embedded", "hardware-support", "no-std"]
-description = "Low level access to RISCV processors"
+description = "Low level access to RISC-V processors"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 
diff --git a/src/lib.rs b/src/lib.rs
index a73ed12..761d2d8 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,4 +1,4 @@
-//! Low level access to RISCV processors
+//! Low level access to RISC-V processors
 //!
 //! This crate provides:
 //!
diff --git a/src/register/mod.rs b/src/register/mod.rs
index 0e8c009..47914b8 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -1,4 +1,4 @@
-//! RISCV CSR's
+//! RISC-V CSR's
 //!
 //! The following registers are not available on 64-bit implementations.
 //!