vexriscv-rust/Cargo.toml

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[package]
name = "riscv"
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version = "0.3.0"
repository = "https://github.com/rust-embedded/riscv"
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authors = ["David Craven <david@craven.ch>"]
categories = ["embedded", "hardware-support", "no-std"]
description = "Low level access to RISCV processors"
keywords = ["riscv", "register", "peripheral"]
license = "ISC"
[dependencies]
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bare-metal = "0.2.0"
bit_field = "0.9.0"
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[features]
inline-asm = []