vexriscv-rust/Cargo.toml

[package]
name = "vexriscv"
version = "0.0.1"
repository = "https://github.com/xobs/vexriscv-rust"
authors = ["Sean Cross <sean@xobs.io>", "The RISC-V Team <risc-v@teams.rust-embedded.org>"]
categories = ["embedded", "hardware-support", "no-std", "vexriscv"]
description = "Low level access to the VexRiscv processor"
keywords = ["riscv", "register", "peripheral", "vexriscv"]
license = "ISC"

[dependencies]
bare-metal = ">=0.2.0,<0.2.5"
bit_field = "0.9.0"

[features]
inline-asm = []
Initial commit. 2017-09-19 22:04:12 +08:00			`[package]`
vexriscv: clone from riscv crate Base the vexriscv crate on the riscv crate, but add vexriscv-specific instructions. Signed-off-by: Sean Cross <sean@xobs.io> 2019-12-28 18:11:12 +08:00			`name = "vexriscv"`
			`version = "0.0.1"`
			`repository = "https://github.com/xobs/vexriscv-rust"`
			`authors = ["Sean Cross <sean@xobs.io>", "The RISC-V Team <risc-v@teams.rust-embedded.org>"]`
			`categories = ["embedded", "hardware-support", "no-std", "vexriscv"]`
			`description = "Low level access to the VexRiscv processor"`
			`keywords = ["riscv", "register", "peripheral", "vexriscv"]`
Initial commit. 2017-09-19 22:04:12 +08:00			`license = "ISC"`

			`[dependencies]`
Do not use bare-metal v0.2.5 (changes MSRV) 2019-09-06 00:53:02 +08:00			`bare-metal = ">=0.2.0,<0.2.5"`
add S-Mode registers - use macros to simplify CSR ops - use crate 'bit_field' to make bits operation clear 2018-11-09 22:42:46 +08:00			`bit_field = "0.9.0"`
Add inline-asm feature. 2018-08-12 13:56:17 +08:00
			`[features]`
vexriscv: clone from riscv crate Base the vexriscv crate on the riscv crate, but add vexriscv-specific instructions. Signed-off-by: Sean Cross <sean@xobs.io> 2019-12-28 18:11:12 +08:00			`inline-asm = []`