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ptbal updates 

Signed-off-by: Kai Dietze <kai.dietze@ptb.de>
master
Robert Jördens 2021-04-26 17:07:55 +02:00
parent 63b074510a
commit f1834ddcb1
1 changed files with 32 additions and 10 deletions
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42
ptbal.json
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@ -1,49 +1,71 @@
{
"_description": "Kasli variant for PTB Schmidt Aluminum clock",
"_description": "PTB IQLOC2",
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "ptbal",
"hw_rev": "v1.1",
"ext_ref_frequency": 10e6,
"base": "standalone",
"core_addr": "192.168.0.5",
"vendor": "QUARTIQ",
"peripherals": [
{
"type": "dio",
"board": "DIO_BNC",
"hw_rev": "v1.2",
"ports": [0],
"bank_direction_low": "input",
"bank_direction_high": "output"
"bank_direction_high": "input",
"edge_counter": true
},
{
"type": "dio",
"board": "DIO_BNC",
"hw_rev": "v1.2",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"hw_rev": "v1.2",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "urukul",
"type": "dio",
"board": "DIO_SMA",
"hw_rev": "v1.2",
"ports": [3],
"clk_sel": 0,
"refclk": 100e6,
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "urukul",
"ports": [4],
"clk_sel": 1,
"hw_rev": "v1.3",
"refclk": 125e6,
"pll_n": 40
},
{
"type": "urukul",
"ports": [5, 4],
"clk_sel": 0,
"refclk": 100e6,
"ports": [5],
"hw_rev": "v1.1",
"clk_sel": 1,
"refclk": 125e6,
"pll_n": 40
},
{
"type": "urukul",
"ports": [6],
"hw_rev": "v1.1",
"variant": "AD9912",
"dds": "ad9912",
"clk_sel": 0,
"refclk": 100e6,
"clk_sel": 1,
"refclk": 125e6,
"pll_n": 10
},
{