From f1834ddcb10cef8c89b49221d8688acf4aa32dc9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Mon, 26 Apr 2021 17:07:55 +0200
Subject: [PATCH] ptbal updates

Signed-off-by: Kai Dietze <kai.dietze@ptb.de>
---
 ptbal.json | 42 ++++++++++++++++++++++++++++++++----------
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/ptbal.json b/ptbal.json
index 3c69429..d0982a8 100644
--- a/ptbal.json
+++ b/ptbal.json
@@ -1,49 +1,71 @@
 {
-    "_description": "Kasli variant for PTB Schmidt Aluminum clock",
+    "_description": "PTB IQLOC2",
     "target": "kasli",
+    "min_artiq_version": "6.0",
     "variant": "ptbal",
     "hw_rev": "v1.1",
+    "ext_ref_frequency": 10e6,
     "base": "standalone",
+    "core_addr": "192.168.0.5",
     "vendor": "QUARTIQ",
     "peripherals": [
         {
             "type": "dio",
+            "board": "DIO_BNC",
+            "hw_rev": "v1.2",
             "ports": [0],
             "bank_direction_low": "input",
-            "bank_direction_high": "output"
+            "bank_direction_high": "input",
+            "edge_counter": true
         },
         {
             "type": "dio",
+            "board": "DIO_BNC",
+            "hw_rev": "v1.2",
             "ports": [1],
             "bank_direction_low": "output",
             "bank_direction_high": "output"
         },
         {
             "type": "dio",
+            "board": "DIO_SMA",
+            "hw_rev": "v1.2",
             "ports": [2],
             "bank_direction_low": "output",
             "bank_direction_high": "output"
         },
         {
-            "type": "urukul",
+            "type": "dio",
+            "board": "DIO_SMA",
+            "hw_rev": "v1.2",
             "ports": [3],
-            "clk_sel": 0,
-            "refclk": 100e6,
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "ports": [4],
+            "clk_sel": 1,
+            "hw_rev": "v1.3",
+            "refclk": 125e6,
             "pll_n": 40
         },
         {
             "type": "urukul",
-            "ports": [5, 4],
-            "clk_sel": 0,
-            "refclk": 100e6,
+            "ports": [5],
+            "hw_rev": "v1.1",
+            "clk_sel": 1,
+            "refclk": 125e6,
             "pll_n": 40
         },
         {
             "type": "urukul",
             "ports": [6],
+            "hw_rev": "v1.1",
+            "variant": "AD9912",
             "dds": "ad9912",
-            "clk_sel": 0,
-            "refclk": 100e6,
+            "clk_sel": 1,
+            "refclk": 125e6,
             "pll_n": 10
         },
         {