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Add Urukul PLL lock timeout failure 

Signed-off-by: Egor Savkin <es@m-labs.hk>
pull/2/head
Egor Savkin 2023-03-27 12:23:13 +08:00
parent 8648e60009
commit 716b368319
2 changed files with 12 additions and 2 deletions
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2
src/hw/clocker.md
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@ -19,7 +19,7 @@ Put the `ext_ref_frequency` field into the JSON description if the Kasli is goin
On peripherals you should choose `"clk_sel": 2` on connected devices. On peripherals you should choose `"clk_sel": 2` on connected devices.
## Setup ## Setup external clocker
For tests, you may need an external RF generator, depending on customer needs. For tests, you may need an external RF generator, depending on customer needs.
Here is example setup for SynthNV RF signal generator: Here is example setup for SynthNV RF signal generator:

12
src/hw/urukul.md
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@ -102,4 +102,14 @@ and if it is connected to the [Clocker](clocker.md), check that clocker receives
ValueError: Urukul proto_rev mismatch ValueError: Urukul proto_rev mismatch
``` ```
Check the ports are connected respectively to the JSON description. Check the ports are connected respectively to the JSON description.
### PLL lock timeout
```pycon
ValueError: PLL lock timeout
```
This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly and `EXT`/`INT` pin
matches real clocker source.