M-Labs/saymapp
2
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

merge README.md

Browse Source
This commit is contained in:
Joe Britton 2019-01-14 11:20:03 -05:00
commit fcdd410963
2 changed files with 3 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -1,2 +0,0 @@
# saymapp
Sayma Project Plan

10
pp.md
View File

@ -185,8 +185,7 @@ Use SAWG v1 with minimal modification to demonstrate Sayma v2 hardware. SAWG v2
# Hardware Developer # Hardware Developer
The Hardware Developer is responsible for hardware design and manufacturing. Testing responsibilities of the Hardware Developer are those detailed in HT3. The Hardware Developer is responsible for hardware design and manufacturing. Testing responsibilities of the Hardware Developer are those detailed in HT3.
The Hardware Developer has deliverables designated HTn. Written progress reports The Hardware Developer has deliverables designated HTn. Written progress reports by the 1st of the month.
- on the 1st and 15th of the month
## __HT1__ high level design ## __HT1__ high level design
High-level schematics for all PCBs to include component part numbers, high-level component interconnection, power budget, high-level layout of all PCBs including location of ICs, board-to-board headers, RF shielding, heat sinks, mechanical support and front panel design. Post design files to github and tag. Participate in design review on github. High-level schematics for all PCBs to include component part numbers, high-level component interconnection, power budget, high-level layout of all PCBs including location of ICs, board-to-board headers, RF shielding, heat sinks, mechanical support and front panel design. Post design files to github and tag. Participate in design review on github.
@ -309,8 +308,7 @@ HT5 delivery is complete when UMD confirms receipt of the demonstration system /
# Integration and Timing Developer # Integration and Timing Developer
An Integration and Timing Developer is responsible for certain aspects of hardware integration and testing as detailed in this section. An Integration and Timing Developer is responsible for certain aspects of hardware integration and testing as detailed in this section.
This developer has one deliverable OT1. Written progress reports This developer has one deliverable OT1. Written progress reports by the 1st of the month.
- on the 1st and 15th of the month
## __OT1__ integration and timing ## __OT1__ integration and timing
@ -368,9 +366,7 @@ The Software and Gateware Developer is responsible for gateware and software nee
All MTk items include support of code in ARTIQ for 3 years from start of contract including documentation of public APIs, maintenance of developed CI infrastructure, publication of CI results. All MTk items include support of code in ARTIQ for 3 years from start of contract including documentation of public APIs, maintenance of developed CI infrastructure, publication of CI results.
The developer’s work consists of deliverables MTk below. Written progress reports are due The developer’s work consists of deliverables MTk below. Written progress reports are due by the 1st of the month.
- on 1st and 15th of the month
- on 1st of the month after OT1 and HT5 are complete
## __MT1__ SAWG ## __MT1__ SAWG