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merge RJ patch from Jan 11

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Joe Britton 2019-01-13 18:50:28 -05:00
parent 5e77325f39
commit 2bd0add400
1 changed files with 11 additions and 12 deletions
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pp.md
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@ -70,7 +70,7 @@ The original SAWG was developed by M-Labs for Sayma v1.0. Here, "v1" refers to S
- synchronization: none
- functionality in 1st Nyquist zone
- 240 MHz is max RF out
- f1, f2: +/- 125 MHz modulation, +/- 100 MHz usable within anti-aliasing filter bandwidth
- f1, f2: 150 MHz modulation, +/- 60 MHz anti-aliasing filter bandwidth
### SAWG v2.0
This is an extension of SAWG v1.0 with a 1 GSPS data rate and with board-board synchronization.
@ -78,10 +78,10 @@ This is an extension of SAWG v1.0 with a 1 GSPS data rate and with board-board s
- dac data rate 1.0 GSPS
- f_dac_clk = 2.0 GHz (2X interpolation)
- synchronization: new Sayma v2 sysref scheme
- support 2 RF channels per DAC
- support 2 RF channels per DAC (!)
- functionality in 1st Nyquist
- 400 MHz is max RF out
- f1, f2: +/- 125 MHz modulation, +/- 100 MHz usable within anti-aliasing filter bandwidth
- f1, f2: 125 MHz modulation, +/- 50 MHz anti-aliasing filter bandwidth
### SAWG v2.1
This is an extension of SAWG v2.0 that includes improvements in performance and gateware utilization.
@ -109,7 +109,7 @@ Deterministic phase alignment between DACs on separate Sayma PCBs between power
- Remove HMC7043, add components needed to generate MGTREFCLK.
- Test conditions
- SAWG output on all channels on two Sayma boards, 400 MHz continuous RF
- Sayma-local TTL output at 75 MHz
- Sayma-local TTL output at 62.5 MHz
- using existing RTIO infrastructure and TTL PHY
- laboratory temperature stability +/- 0.5 C
- Cycle crate power 100 times
@ -254,6 +254,7 @@ Expectations for testing of all stuffed PCBs.
- AMC backplane ethernet PRBS at 1 GSPS
- SFP loop-back PRBS at 1 Gb/s
- FMC loop-back PRBS [TODO ____ data rate]
- Realistic FPGA fabric load and clock activity
- MMC configuration including power supply sequencing and IPMI
- Hardware Developer shall test MMC firmware on TS7 system prior to distribution.
- If errors arise after initial distribution Hardware Developer shall debug and test on TS2.
@ -271,7 +272,7 @@ HT3 delivery is complete when the Software and Gateware Developer and Integratio
## __HT4__ documentation and MMC
- Support system integrators by github Issue system.
- Develop and document fixes for hardware bugs.
- If bug fixes are substantial (eg replacing multi-pin SMD), system integrators may at their option return boards to the Hardware Developer for repair. System integrator pays shipping inbound, Hardware Developer pays shipping outbound.
- If bug fixes are substantial (eg replacing multi-pin SMD), system integrators may at their option return boards to the Hardware Developer for repair. System integrator pays shipping inbound, Hardware Developer pays shipping outbound. Limit to 10 shipping round trips.
- Each board should have a serial number, and a wiki page where everyone who reworks the board has to document what they did. Other notes about that particular board and its specific bugs can be added there.
- MMC and Exar configuration
- Publish source on github within sinara-hw domain.
@ -402,9 +403,9 @@ Each MTk includes a short report and option to implement.
## __MT2__ Sayma v2 Planning
- __M21__ Develop fixed test pattern generator (4-point sine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG.
- __M21__ Develop fixed test pattern generator (12-point cosine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG.
- __MT22__ Review and verify Sayma v2 design from the FPGA perspective. Do this by building a stub ARTIQ target and test compilation -- depends on obtaining netlist for FPGAs from Hardware Developer (HT2). This will verify IO assignments and usage patterns around the following subsystems
- __MT22__ Review and verify Sayma v2 design from the FPGA perspective. Do this by building a stub ARTIQ target and test compilation -- depends on obtaining netlist for FPGAs from Hardware Developer (HT2). This will verify IO assignments and usage patterns around the following subsystems to the level currently used in ARTIQ
- ethernet
- transceivers
- clocking
@ -414,7 +415,7 @@ Each MTk includes a short report and option to implement.
- AFE ports
- FMC ports
- __MT23__ Review of the scheme for synchronization between pairs of Sayma boards.
- __MT23__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme.
@ -432,23 +433,21 @@ recovery on RTM, JESD204B deterministic latency/synchronization.
- UARTs
- SDRAM
- ethernet
- I2C EEPROM (MAC address and board serial numbers)
- I2C EEPROM (MAC address and board serial numbers) (through USB-FTDI?)
- clocking (including DRTIO clock recovery)
- RTIO transcievers
- RTIO SERDES TTL
- FMC connectors
[- TODO anything missing?]
- build infrastructure and packaging
- __M34__ Support for Sayma_RTM to include the following
- power up
- boot tasks including JTAG (slave serial) loading of flash & FPGA
- boot tasks including slave serial loading of FPGA
- RTM clocking
- develop DRTIO for AMC FPGA to RTM FPGA link
- SPI to HMC830 and AD9154
- AFE interfaces
- build infrastructure and packaging
[- TODO anything missing?]
- dependency: M33
- __M35__ Support for BaseMod to include the following