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remove advanced SDRAM tests

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Joe Britton 2019-03-07 17:27:13 -05:00
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@ -375,21 +375,6 @@ MT1 is a port of SAWG v1.0 designed for Sayma v1 to Sayma v2.
- __M2.03__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme. - __M2.03__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme.
- __ M2.04__ SDRAM test suite
In support of HT3 tests conducted by Hardware Developer, write
gateware module to test SDRAM power consumption and signal integrity.
The test shall be developed in coordination with Hardware Developer and with
their HT3 test workflow in mind.
- maximum I/O bandwidth (64Gbps), refresh disabled
- continuous precharge/activate cycles in one bank at the maximum rate
permitted by the chip and the available command bandwidth
- continuous data transfers on other banks with the following pattern
- 0x5555... / 0xaaaa... to test for cross talk
- 0xffff... / 0x0000... to test for ground bounce
- one row in the data test bank permanently open
Adapt to be included in ARTIQ built-in self-test suite.
## __MT3__ Sayma v2 ARTIQ Support ## __MT3__ Sayma v2 ARTIQ Support