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remove SAWG v2.1

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Joe Britton 2019-03-07 17:22:24 -05:00
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@ -92,14 +92,6 @@ This is an extension of SAWG v1.0 with a 1 GSPS data rate. This milestone also
- 400 MHz is max RF out
- f1, f2: 125 MHz modulation, +/- 50 MHz anti-aliasing filter bandwidth
__SAWG v2.1 milestone__
This is an extension of SAWG v2.0 that includes improvements in performance and gateware utilization.
- support for 4 RF channels per DAC
- spurious frequency components due to DSP: < -70 dBc at full amplitude, constant frequency
- improvements as detailed in MT1
# Sayma v2 Diffs
When diff also applies for [Metlino](https://github.com/sinara-hw/Metlino/issues) it is noted.
@ -361,31 +353,12 @@ The developer’s work consists of deliverables MTk below. Written progress repo
## __MT1__ SAWG
MT1 is a port of SAWG v1.0 designed for Sayma v1 to Sayma v2. Additional improvements in SAWG are also specified. The improvements include consideration of future modulation by RTIO and by Modulation by local DSP.
Each MTk includes a short report and option to implement.
MT1 is a port of SAWG v1.0 designed for Sayma v1 to Sayma v2.
- __M1.01__ Support SAWG v2.0
- Develop code for Sayma v2 SAWG+JESD+fpga clock tree at 1 GSPS.
- Implement new Sayma v2 sysref synchronization scheme.
- __M1.02__ SAWG v2.1 element: Measure resource usage and limit number of channels if unable to fit.
- __M1.03__ SAWG v2.1 element: Evaluate clocking SAWG or parts of it at 250 MHz (2x f_rtio)
- __M1.04__ SAWG v2.1 element: Determine number of CORDIC stages, width, phase resolution to achieve a specified spur suppression under specified conditions
- __M1.05__ SAWG v2.1 element: Design transaction based SAWG RTIO protocol (rewrite protocol to stage interpolator settings over one or few non-concurrent RTIO output channels, then activate synchronously with a single RTIO output event). Discuss and determine data partitioning among interpolators and SAWG channels.
- __M1.06__ SAWG v2.1 element: Design fractional representation of high-order spline interpolator coefficients (i.e. instead of 64 bits, just 16 denominator + 16 numerator bits for the 3rd order spline coefficient). This also allows getting rid of the SAWG clock stretcher that was never officially supported.
- __M1.07__ SAWG v2.1 element: Evaluate SAWG DUC redesign with 3 or 4 bit frequency and phase resolution based on multipliers instead of parallel cordics.
- __M1.08__ SAWG v2.1 element: Evaluate resource consumption of modulation ports for after spline interpolators.
- Multiplicative for amplitude, additive and saturating for frequency and phase.
- No support for configurable clipping amplitude at modulation summing junctions. Clipping is always on.
## __MT2__ Sayma v2 Planning
- __M2.01__ Develop fixed test pattern generator (12-point cosine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG.
@ -422,7 +395,7 @@ Adapt to be included in ARTIQ built-in self-test suite.
- __M3.01__ Review the code emerging from O14 and O15. Support merge into ARTIQ. Aspects included in review: DRTIO-on-RTM, DRTIO clock recovery on RTM, JESD204B deterministic latency/synchronization and DDMTD.
- __M3.02__ Work with TPOC to develop test cases for SAWG v2.1 with ST1 and ST2 in mind. Split into manual test cases and tests amendable to continuous integration (CI). Procure hardware needed for hardware-in-the-loop tests.
- __M3.02__ Work with TPOC to develop test cases for SAWG v2.0 with ST1 and ST2 in mind. Split into manual test cases and tests amendable to continuous integration (CI). Procure hardware needed for hardware-in-the-loop tests.
- __M3.03__ Support for Sayma_AMC to include the following
- power up
@ -463,18 +436,12 @@ Adapt to be included in ARTIQ built-in self-test suite.
- ensure passage of tests ST1, ST2, ST3 and ST4
- dependencies: M3.06, O1.04
- __M3.08__ SAWG v2.1
- ensure proper implementation of features in SAWG v2.1
- confirm that ST1, ST2, ST3 and ST4 tests still pass
- dependency: M3.07
- __M3.09__ Documentation
- integrate manual and automated CI tests into ARTIQ infrastructure
- document manual and automated CI tests, hardware-in-the-loop infrastructure
- document CI infrastructure and how to run CI tests
- support Hardware Developer and TPOC in reproducing CI tests
- document Sayma v2 ARTIQ support
- SAWG v2.1 ARTIQ Python API
- document underlying DSP architecture
- __M3.11__ Support Hardware Developer on HT5