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fix formatting:

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Joe Britton 2019-03-05 11:53:35 -05:00
parent 20281434ca
commit 93e7303a24
1 changed files with 3 additions and 3 deletions
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pp.md
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@ -80,7 +80,7 @@ The original SAWG was developed by M-Labs for Sayma v1.0. Here, "v1" refers to S
- 240 MHz is max RF out
- f1, f2: 150 MHz modulation, +/- 60 MHz anti-aliasing filter bandwidth
__SAWG v2.0 milestone_
__SAWG v2.0 milestone__
This is an extension of SAWG v1.0 with a 1 GSPS data rate. This milestone also includes board-board synchronization.
- f_rtio = f_dac_ref = 125 MHz (same as for Kasli)
@ -333,7 +333,7 @@ Code submitted for inclusion in ARTIQ shall comply with CONTRIBUTING.rst (https:
- __O1.03__ participate in HT2 design review
- __O1.04_ based on O1.01, ensure passage of ST3 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1. Note that this test is short of the full ST3 test which specifies a pair of Sayma v2 boards.
- __O1.04__ based on O1.01, ensure passage of ST3 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1. Note that this test is short of the full ST3 test which specifies a pair of Sayma v2 boards.
- Write and document code. Generate pull request.
- __O1.05__ ADF4356
@ -404,7 +404,7 @@ Each MTk includes a short report and option to implement.
- __M2.03__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme.
- __ M2.04__ SDRAM test suite
- __M2.04__ SDRAM test suite
In support of HT3 tests conducted by Hardware Developer, write
gateware module to test SDRAM power consumption and signal integrity.