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clean up formatting, clarify inclusion of DDMTD

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Joe Britton 2019-01-18 14:09:33 -05:00
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@ -12,7 +12,7 @@ ARL will serve as Technical Point of Contact (TPOC) for the contracts.
## Tasks
Developer tasks are labeled HTj, Ojk and Mjk (jk integers) and are not divisible. If a task or feature is not assigned to a Developer then that Developer is not responsible for it.
Developer tasks are labeled HTj, Oj.k and Mj.k (jk integers) and are not divisible. If a task or feature is not assigned to a Developer then that Developer is not responsible for it.
## Design Review
@ -38,6 +38,9 @@ If shipment budget or hardware-flaw budget is exhausted the Developer may
- cancel dependent task(s) and receive payment for up to 50% task cost
- renegotiate contract terms for dependent task(s) with TPOC
## Handling Failures Unrelated to Hardware
Hardware Developer task HT5 depends on tasks from Software and Gateware Developer and Integration and Timing Developer. If these dependencies are not met the Hardware Developer may after discussion with TPOC ship demonstration to UMD without successful completion of a subset of the following tests ST1, ST2, ST3 and ST4 as dictated by the missing dependency.
# Definitions
Let __TS-MTCA__ be a micro TCA crate configured as follows:
- 1 NAT NATIVE-R5 (or -R9)
@ -332,7 +335,7 @@ Code submitted for inclusion in ARTIQ shall comply with CONTRIBUTING.rst (https:
- Write and test ADF4356 driver.
- Write and document code. Generate pull request.
- __O1.06__ in support of clock distribution modeled after White Rabbit (WR, DDMTD), specify layout of Si549 and related components
- __O1.06__ in support of clock distribution modeled after White Rabbit (WR, DDMTD), specify layout of Si549 and related components.
OT1 delivery is complete when the Integration and Timing Developer completes and documents the above tasks.
@ -413,8 +416,7 @@ Adapt to be included in ARTIQ built-in self-test suite.
## __MT3__ Sayma v2 ARTIQ Support
- __M3.01__ Review the code emerging from O14 and O15. Support merge into ARTIQ. Aspects included in review: DRTIO-on-RTM, DRTIO clock recovery on RTM, JESD204B deterministic latency/synchronization.
[TODO: does this include DDMTD?]
- __M3.01__ Review the code emerging from O14 and O15. Support merge into ARTIQ. Aspects included in review: DRTIO-on-RTM, DRTIO clock recovery on RTM, JESD204B deterministic latency/synchronization and DDMTD.
- __M3.02__ Work with TPOC to develop test cases for SAWG v2.1 with ST1 and ST2 in mind. Split into manual test cases and tests amendable to continuous integration (CI). Procure hardware needed for hardware-in-the-loop tests.