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clean up formatting, clarify inclusion of DDMTD

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Joe Britton 2019-01-18 11:20:18 -05:00
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@ -181,11 +181,10 @@ Use SAWG v1 with minimal modification to demonstrate Sayma v2 hardware. SAWG v2
- Layout so that uTCA Port0 and SFP can be driven by M88E1512 or by GTH transceiver on FPGA. Use coupling capacitors to choose which.
- Also applies to Metlino.
------------
# Hardware Developer
The Hardware Developer is responsible for hardware design and manufacturing. Testing responsibilities of the Hardware Developer are those detailed in HT3.
The Hardware Developer has deliverables designated HTn. Written progress reports by the 1st of the month.
@ -263,8 +262,6 @@ Expectations for testing of all stuffed PCBs.
- If errors arise after initial distribution Hardware Developer shall debug and test on TS2.
- Publish MCH configuration configuration file used for these tests with TS-MTCA and NATIVE-R5.
Distribute hardware to system integrators:
- Software and Gateware Developer: 2 AMC, 2 RTM, 4 AFE, 1 Metlino
- Integration and Timing Developer: 2 AMC, 2 RTM, 4 AFE, 1 Metlino
@ -308,6 +305,7 @@ HT5 delivery is complete when UMD confirms receipt of the demonstration system /
- Update schematics and layout to remedy bugs.
- Publish to github list of factory acceptance tests including expected results and failure criteria.
----
# Integration and Timing Developer
An Integration and Timing Developer is responsible for certain aspects of hardware integration and testing as detailed in this section.
@ -316,50 +314,30 @@ This developer has one deliverable OT1. Written progress reports by the 1st of t
## __OT1__ integration and timing
Dependency: Software and Gateware Developer is responsible for supplying AD9154 support at the level of M25 and M32. Integration and Timing Developer will handle debugging of ADF4356 and AD9154 as relates to ST4.
Dependency: Software and Gateware Developer is responsible for supplying AD9154 support at the level of M3.04 and M3.06. Integration and Timing Developer will handle debugging of ADF4356 and AD9154 as relates to ST4.
Code submitted for inclusion in ARTIQ shall comply with CONTRIBUTING.rst (https://github.com/m-labs/artiq/blob/master/CONTRIBUTING.rst).
- __O11__ implement DAC-FPGA synchronization with 2 GHz DAC clock (1 GSPS data rate).
- __O1.01__ implement DAC-FPGA synchronization with 2 GHz DAC clock (1 GSPS data rate).
- __O12__ participate in HT1 and HT1.5 design reviews
- __O1.02__ participate in HT1 and HT1.5 design reviews
- __O13__ participate in HT2 design review
- __O1.03__ participate in HT2 design review
- __O14__ Based on O11, demonstrate ST4 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1.
- __O1.04_ Based on O11, demonstrate ST4 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1.
- Write and document code. Generate pull request.
- __O15__ ADF4356
- __O1.05__ ADF4356
- Measure phase determinism of ADF4356.
- Write and test ADF4356 driver.
- Write and document code. Generate pull request.
- __O16__ in support of a future clock distribution scheme modeled after White Rabbit (WR, DDMTD), specify layout of Si549 and related components
[TODO: How to support this if at all? - Write and document code. Generate pull request.]
OT1 delivery is complete when the Integration and Timing Developer completes and documents tasks O11 to O16.
- __O1.06__ in support of clock distribution modeled after White Rabbit (WR, DDMTD), specify layout of Si549 and related components
OT1 delivery is complete when the Integration and Timing Developer completes and documents the above tasks.
----
# Software and Gateware Developer
@ -401,8 +379,6 @@ Each MTk includes a short report and option to implement.
- No support for configurable clipping amplitude at modulation summing junctions. Clipping is always on.
## __MT2__ Sayma v2 Planning
- __M2.01__ Develop fixed test pattern generator (12-point cosine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG.
@ -504,6 +480,7 @@ Adapt to be included in ARTIQ built-in self-test suite.
----------
# Project Organization
ARL/UMD will fund and manage contracts with @jbqubit serving as technical point of contact (TPOC).
New github repositories were setup for each component of the Sayma system.