27 lines
918 B
Diff
27 lines
918 B
Diff
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diff --git a/src/migen_axi/cores/ps7.py b/src/migen_axi/cores/ps7.py
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index 616b65c..ee56d19 100644
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--- a/src/migen_axi/cores/ps7.py
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+++ b/src/migen_axi/cores/ps7.py
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@@ -396,9 +396,6 @@ class PS7(Module):
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self.ddr_arb = Signal(4)
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self.mio = Signal(54)
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- self.clock_domains.cd_sys = ClockDomain()
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- self.clock_domains.cd_por = ClockDomain(reset_less=True)
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-
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self.dma0 = dmac_bus.Interface(name="dma0")
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self.dma1 = dmac_bus.Interface(name="dma1")
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self.dma2 = dmac_bus.Interface(name="dma2")
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@@ -491,11 +488,6 @@ class PS7(Module):
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]
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self.fclk = fclk_rec()
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- # fclk.reset_n considered async
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- self.specials += [
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- AsyncResetSynchronizer(self.cd_sys, ~self.fclk.reset_n[0]),
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- bufg([self.fclk.clk[0], ClockSignal()]),
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- ]
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self.comb += self.fclk.clktrig_n.eq(0)
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ftmd = ftmd_rec()
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