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11
README.md
11
README.md
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@ -4,18 +4,19 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
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## Progress
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- Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen
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- [ ] Implement the core in nMigen
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- - [ ] `rtio.core`
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- - [ ] `rtio.cri`
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- - [x] `rtio.rtlink`
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- - [x] `rtio.channel`
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- - [ ] `rtio.rtlink`
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- - [ ] `rtio.channel`
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- - [ ] `rtio.sed.core`
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- - [x] `rtio.sed.layouts`
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- - [x] `rtio.sed.lane_distributor`
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- - [ ] `rtio.sed.layouts`
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- - [ ] `rtio.sed.lane_distributor`
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- - [ ] `rtio.sed.fifos`
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- - [ ] `rtio.sed.gates`
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- - [ ] `rtio.sed.output_driver`
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- - [x] `rtio.sed.output_network`
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- - [ ] `rtio.sed.output_network`
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- - [ ] `rtio.input_collector`
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- [ ] Add suitable assertions for verification (BMC / unbounded proof?)
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@ -0,0 +1 @@
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@ -1,36 +1 @@
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import warnings
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from rtio import rtlink
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class Channel:
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def __init__(self, interface, probes=None, overrides=None,
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ofifo_depth=None, ififo_depth=64):
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if probes is None:
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probes = []
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if overrides is None:
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overrides = []
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self.interface = interface
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self.probes = probes
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self.overrides = overrides
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if ofifo_depth is None:
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ofifo_depth = 64
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else:
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warnings.warn("ofifo_depth is deprecated", FutureWarning)
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self.ofifo_depth = ofifo_depth
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self.ififo_depth = ififo_depth
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@classmethod
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def from_phy(cls, phy, **kwargs):
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probes = getattr(phy, "probes", [])
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overrides = getattr(phy, "overrides", [])
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return cls(phy.rtlink, probes, overrides, **kwargs)
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class LogChannel:
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"""A degenerate channel used to log messages into the analyzer."""
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def __init__(self):
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self.interface = rtlink.Interface(rtlink.OInterface(32))
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self.probes = []
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self.overrides = []
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@ -0,0 +1 @@
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125
rtio/cri.py
125
rtio/cri.py
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@ -1,126 +1 @@
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from nmigen import *
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from nmigen.utils import *
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from nmigen.hdl.rec import *
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"""Common RTIO Interface"""
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# CRI write happens in 3 cycles:
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# 1. set timestamp and channel
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# 2. set other payload elements and issue write command
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# 3. check status
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commands = {
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"nop": 0,
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"write": 1,
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# i_status should have the "wait for status" bit set until
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# an event is available, or timestamp is reached.
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"read": 2,
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# targets must assert o_buffer_space_valid in response
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# to this command
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"get_buffer_space": 3
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}
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layout = [
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("cmd", 2, DIR_FANOUT),
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# 8 MSBs of chan_sel = routing destination
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# 16 LSBs of chan_sel = channel within the destination
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("chan_sel", 24, DIR_FANOUT),
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("o_timestamp", 64, DIR_FANOUT),
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("o_data", 512, DIR_FANOUT),
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("o_address", 8, DIR_FANOUT),
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# o_status bits:
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# <0:wait> <1:underflow> <2:destination unreachable>
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("o_status", 3, DIR_FANIN),
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# pessimistic estimate of the number of outputs events that can be
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# written without waiting.
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# this feature may be omitted on systems without DRTIO.
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("o_buffer_space_valid", 1, DIR_FANIN),
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("o_buffer_space", 16, DIR_FANIN),
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("i_timeout", 64, DIR_FANOUT),
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("i_data", 32, DIR_FANIN),
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("i_timestamp", 64, DIR_FANIN),
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# i_status bits:
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# <0:wait for event (command timeout)> <1:overflow> <2:wait for status>
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# <3:destination unreachable>
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# <0> and <1> are mutually exclusive. <1> has higher priority.
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("i_status", 4, DIR_FANIN),
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]
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class Interface(Record):
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def __init__(self, **kwargs):
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super().__init__(layout, **kwargs)
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# Skip KernelInitiator for now
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class CRIDecoder(Elaboratable):
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def __init__(self, slaves=2, master=None, mode="async", enable_routing=False):
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if isinstance(slaves, int):
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slaves = [Interface() for _ in range(slaves)]
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if master is None:
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master = Interface()
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self.slaves = slaves
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self.master = master
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self.mode = mode
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self.enable_routing = enable_routing
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def elaborate(self, platform):
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m = Module()
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# routing
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if self.enable_routing:
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destination_unreachable = Interface()
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m.d.comb += destination_unreachable.o_status.eq(4)
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m.d.comb += destination_unreachable.i_status.eq(8)
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self.slaves = self.slaves[:]
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self.slaves.append(destination_unreachable)
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target_len = 2 ** (len(slaves) - 1).bit_length()
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self.slaves += [destination_unreachable] * (target_len - len(slaves))
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slave_bits = bits_for(len(self.slaves) - 1)
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selected = Signal(slave_bits)
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if self.enable_routing:
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routing_table = Memory(slave_bits, 256)
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if self.mode == "async":
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rtp_decoder_rdport = routing_table.read_port()
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rtp_decoder_wrport = routing_table.write_port()
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elif self.mode == "sync":
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rtp_decoder_rdport = routing_table.read_port(clock_domain="rtio")
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rtp_decoder_wrport = routing_tables.write_port(clock_domain="rtio")
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else:
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raise ValueError
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m.submodules.rtp_decoder_rdport = rtp_decoder_rdport
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m.submodules.rtp_decoder_wrport = rtp_decoder_wrport
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m.d.comb += rtp_decoder_rdport.addr.eq(self.master.chan_sel[16:])
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m.d.comb += selected.eq(rtp_decoder_rdport.data)
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else:
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m.d.sync += selected.eq(self.master.chan_sel[16:])
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# master -> slave
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for n, slave in enumerate(self.slaves):
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for name, size, direction in layout:
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if direction == DIR_FANOUT and name != "cmd":
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m.d.comb += getattr(slave, name).eq(getattr(self.master, name))
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with m.If(selected == n):
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m.d.comb += slave.cmd.eq(self.master.cmd)
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# slave -> master
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with m.Switch(selected):
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for n, slave in enumerate(self.slaves):
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with m.Case(n):
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for name, size, direction in layout:
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if direction == DIR_FANIN:
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m.d.comb += getattr(self.master, name).eq(getattr(slave, name))
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return m
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# TODO: CRISwitch
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# TODO: CRIInterconnectShared
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# TODO: RoutingTableAccess
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@ -1,97 +1 @@
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from nmigen import *
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class OInterface:
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def __init__(self, data_width, address_width=0,
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fine_ts_width=0, enable_replace=True,
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delay=0):
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self.stb = Signal()
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self.busy = Signal()
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assert 0 <= data_width <= 512
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assert 0 <= address_width <= 8
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assert 0 <= fine_ts_width <= 4
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if data_width:
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self.data = Signal(data_width, reset_less=True)
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if address_width:
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self.address = Signal(address_width, reset_less=True)
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if fine_ts_width:
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self.fine_ts = Signal(fine_ts_width, reset_less=True)
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self.enable_replace = enable_replace
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if delay < 0:
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raise ValueError("only positive delays allowed", delay)
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self.delay = delay
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@classmethod
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def like(cls, other):
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return cls(get_data_width(other),
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get_address_width(other),
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get_fine_ts_width(other),
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other.enable_replace,
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other.delay)
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class IInterface:
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def __init__(self, data_width,
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timestamped=True, fine_ts_width=0, delay=0):
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self.stb = Signal()
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assert 0 <= data_width <= 32
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assert 0 <= fine_ts_width <= 4
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if data_width:
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self.data = Signal(data_width, reset_less=True)
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if fine_ts_width:
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self.fine_ts = Signal(fine_ts_width, reset_less=True)
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assert(not fine_ts_width or timestamped)
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self.timestamped = timestamped
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if delay < 0:
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raise ValueError("only positive delays")
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self.delay = delay
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@classmethod
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def like(cls, other):
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return cls(get_data_width(other),
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other.timestamped,
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get_fine_ts_width(other),
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other.delay)
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class Interface:
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def __init__(self, o, i=None):
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self.o = o
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self.i = i
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@classmethod
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def like(cls, other):
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if other.i is None:
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return cls(OInterface.like(other.o))
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else:
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return cls(OInterface.like(other.o),
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IInterface.like(other.i))
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def _get_or_zero(interface, attr):
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if interface is None:
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return 0
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assert isinstance(interface, (OInterface, IInterface))
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if hasattr(interface, attr):
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return len(getattr(interface, attr))
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else:
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return 0
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def get_data_width(interface):
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return _get_or_zero(interface, "data")
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def get_address_width(interface):
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return _get_or_zero(interface, "address")
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def get_fine_ts_width(interface):
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return _get_or_zero(interface, "fine_ts")
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@ -1,170 +1 @@
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from nmigen import *
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from rtio import cri
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from rtio.sed import layouts
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__all__ = ["LaneDistributor"]
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class LaneDistributor(Elaboratable):
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def __init__(self, lane_count, seqn_width, layout_payload,
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compensation, glbl_fine_ts_width,
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enable_spread=True, quash_channels=[], interface=None):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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if interface is None:
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interface = cri.Interface()
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self.cri = interface
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self.sequence_error = Signal()
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self.sequence_error_channel = Signal(16, reset_less=True)
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# The minimum timestamp that an event must have to avoid triggering
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# an underflow, at the time when the CRI write happens, and to a channel
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# with zero latency compensation. This is synchronous to the system clock
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# domain.
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us_timestamp_width = 64 - glbl_fine_ts_width
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self.minimum_coarse_timestamp = Signal(us_timestamp_width)
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self.output = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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self.lane_count = lane_count
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self.us_timestamp_width = us_timestamp_width
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self.seqn_width = seqn_width
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self.glbl_fine_ts_width = glbl_fine_ts_width
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self.quash_channels = quash_channels
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self.compensation = compensation
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self.enable_spread = enable_spread
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def elaborate(self, platform):
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m = Module()
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o_status_wait = Signal()
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o_status_underflow = Signal()
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m.d.comb += self.cri.o_status.eq(Cat(o_status_wait, o_status_underflow))
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# The core keeps writing events into the current lane as long as timestamps
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# (after compensation) are strictly increasing, otherwise it switches to
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# the next lane.
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# If spread is enabled, it also switches to the next lane after the current
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# lane has been full, in order to maximize lane utilization.
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# The current lane is called lane "A". The next lane (which may be chosen
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# at a later stage by the core) is called lane "B".
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# Computations for both lanes are prepared in advance to increase performance.
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current_lane = Signal(range(self.lane_count))
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# The last coarse timestamp received from the CRI, after compensation.
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# Used to determine when to switch lanes.
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last_coarse_timestamp = Signal(self.us_timestamp_width)
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# The last coarse timestamp written to each lane. Used to detect
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# sequence errors.
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last_lane_coarse_timestamps = Array(Signal(self.us_timestamp_width)
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for _ in range(self.lane_count))
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# Sequence number counter. The sequence number is used to determine which
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# event wins during a replace.
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seqn = Signal(self.seqn_width)
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# distribute data to lanes
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for lio in self.output:
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m.d.comb += lio.seqn.eq(seqn)
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m.d.comb += lio.payload.channel.eq(self.cri.chan_sel[:16])
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m.d.comb += lio.payload.timestamp.eq(self.cri.o_timestamp)
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if hasattr(lio.payload, "address"):
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m.d.comb += lio.payload.address.eq(self.cri.o_address)
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if hasattr(lio.payload, "data"):
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m.d.comb += lio.payload.data.eq(self.cri.o_data)
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# when timestamp and channel arrive in cycle #1, prepare computations
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coarse_timestamp = Signal(self.us_timestamp_width)
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m.d.comb += coarse_timestamp.eq(self.cri.o_timestamp[self.glbl_fine_ts_width:])
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min_minus_timestamp = Signal(Shape(self.us_timestamp_width + 1, True),
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reset_less=True)
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laneAmin_minus_timestamp = Signal.like(min_minus_timestamp)
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laneBmin_minus_timestamp = Signal.like(min_minus_timestamp)
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last_minus_timestamp = Signal.like(min_minus_timestamp)
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current_lane_plus_one = Signal(range(self.lane_count))
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m.d.comb += current_lane_plus_one.eq(current_lane + 1)
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m.d.sync += min_minus_timestamp.eq(self.minimum_coarse_timestamp - coarse_timestamp)
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m.d.sync += laneAmin_minus_timestamp.eq(last_lane_coarse_timestamps[current_lane] - coarse_timestamp)
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m.d.sync += laneBmin_minus_timestamp.eq(last_lane_coarse_timestamps[current_lane_plus_one] - coarse_timestamp)
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m.d.sync += last_minus_timestamp.eq(last_coarse_timestamp - coarse_timestamp)
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# Quash channels are "dummy" channels to which writes are completely ignored.
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# This is used by the RTIO log channel, which is taken into account
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# by the analyzer but does not enter the lanes.
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quash = Signal()
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m.d.sync += quash.eq(0)
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for channel in self.quash_channels:
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with m.If(self.cri.chan_sel[:16] == channel):
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m.d.sync += quash.eq(1)
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assert all(abs(c) < 1 << 14 - 1 for c in self.compensation)
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latency_compensation = Memory(width=14, depth=len(self.compensation), init=self.compensation)
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latency_compensation_rdport = latency_compensation.read_port()
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m.submodules.latency_compensation_rdport = latency_compensation_rdport
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m.d.comb += latency_compensation_rdport.addr.eq(self.cri.chan_sel[:16])
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# cycle #2, write
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compensation = Signal(Shape(14, True))
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m.d.comb += compensation.eq(latency_compensation_rdport.data)
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timestamp_above_min = Signal()
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timestamp_above_last = Signal()
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timestamp_above_laneA_min = Signal()
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timestamp_above_laneB_min = Signal()
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timestamp_above_lane_min = Signal()
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force_laneB = Signal()
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use_laneB = Signal()
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use_lanen = Signal(range(self.lane_count))
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do_write = Signal()
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do_underflow = Signal()
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do_sequence_error = Signal()
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m.d.comb += timestamp_above_min.eq(min_minus_timestamp - compensation < 0)
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m.d.comb += timestamp_above_laneA_min.eq(laneAmin_minus_timestamp - compensation < 0)
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m.d.comb += timestamp_above_laneB_min.eq(laneBmin_minus_timestamp - compensation < 0)
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m.d.comb += timestamp_above_last.eq(last_minus_timestamp - compensation < 0)
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with m.If(force_laneB | ~timestamp_above_last):
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m.d.comb += use_lanen.eq(current_lane_plus_one)
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m.d.comb += use_laneB.eq(1)
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with m.Else():
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m.d.comb += use_lanen.eq(current_lane)
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m.d.comb += use_laneB.eq(0)
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m.d.comb += timestamp_above_lane_min.eq(Mux(use_laneB, timestamp_above_laneB_min, timestamp_above_laneA_min))
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with m.If(~quash & (self.cri.cmd == cri.commands["write"])):
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with m.If(timestamp_above_min):
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with m.If(timestamp_above_lane_min):
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m.d.comb += do_write.eq(1)
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with m.Else():
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m.d.comb += do_sequence_error.eq(1)
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with m.Else():
|
||||
m.d.comb += do_underflow.eq(1)
|
||||
m.d.comb += Array(lio.we for lio in self.output)[use_lanen].eq(do_write)
|
||||
compensated_timestamp = Signal(64)
|
||||
m.d.comb += compensated_timestamp.eq(self.cri.o_timestamp + (compensation << self.glbl_fine_ts_width))
|
||||
with m.If(do_write):
|
||||
m.d.sync += current_lane.eq(use_lanen)
|
||||
m.d.sync += last_coarse_timestamp.eq(compensated_timestamp[self.glbl_fine_ts_width:])
|
||||
m.d.sync += last_lane_coarse_timestamps[use_lanen].eq(compensated_timestamp[self.glbl_fine_ts_width:])
|
||||
m.d.sync += seqn.eq(seqn + 1)
|
||||
for lio in self.output:
|
||||
m.d.comb += lio.payload.timestamp.eq(compensated_timestamp)
|
||||
|
||||
# cycle #3, read status
|
||||
current_lane_writable = Signal()
|
||||
m.d.comb += current_lane_writable.eq(Array(lio.writable for lio in self.output)[current_lane])
|
||||
m.d.comb += o_status_wait.eq(~current_lane_writable)
|
||||
with m.If(self.cri.cmd == cri.commands["write"]):
|
||||
m.d.sync += o_status_underflow.eq(0)
|
||||
with m.If(do_underflow):
|
||||
m.d.sync += o_status_underflow.eq(1)
|
||||
m.d.sync += self.sequence_error.eq(do_sequence_error)
|
||||
m.d.sync += self.sequence_error_channel.eq(self.cri.chan_sel[:16])
|
||||
|
||||
# current lane has been full, spread events by switching to the next.
|
||||
if self.enable_spread:
|
||||
current_lane_writable_r = Signal(reset=1)
|
||||
m.d.sync += current_lane_writable_r.eq(current_lane_writable)
|
||||
with m.If(~current_lane_writable_r & current_lane_writable):
|
||||
m.d.sync += force_laneB.eq(1)
|
||||
with m.If(do_write):
|
||||
m.d.sync += force_laneB.eq(0)
|
||||
|
||||
return m
|
||||
|
|
|
|||
|
|
@ -1,79 +1 @@
|
|||
from nmigen import *
|
||||
from nmigen.utils import *
|
||||
from nmigen.hdl.rec import *
|
||||
|
||||
from rtio import rtlink
|
||||
|
||||
|
||||
def fifo_payload(channels):
|
||||
address_width = max(rtlink.get_address_width(channel.interface.o)
|
||||
for channel in channels)
|
||||
data_width = max(rtlink.get_data_width(channel.interface.o)
|
||||
for channel in channels)
|
||||
|
||||
layout = [
|
||||
("channel", bits_for(len(channels)-1)),
|
||||
("timestamp", 64)
|
||||
]
|
||||
if address_width:
|
||||
layout.append(("address", address_width))
|
||||
if data_width:
|
||||
layout.append(("data", data_width))
|
||||
|
||||
return layout
|
||||
|
||||
|
||||
def seqn_width(lane_count, fifo_depth):
|
||||
# There must be a unique sequence number for every possible event in every FIFO.
|
||||
# Plus 2 bits to detect and handle wraparounds.
|
||||
return bits_for(lane_count*fifo_depth-1) + 2
|
||||
|
||||
|
||||
def fifo_ingress(seqn_width, layout_payload):
|
||||
return [
|
||||
("we", 1, DIR_FANOUT),
|
||||
("writable", 1, DIR_FANIN),
|
||||
("seqn", seqn_width, DIR_FANOUT),
|
||||
("payload", [(a, b, DIR_FANOUT) for a, b in layout_payload])
|
||||
]
|
||||
|
||||
|
||||
def fifo_egress(seqn_width, layout_payload):
|
||||
return [
|
||||
("re", 1, DIR_FANIN),
|
||||
("readable", 1, DIR_FANOUT),
|
||||
("seqn", seqn_width, DIR_FANOUT),
|
||||
("payload", [(a, b, DIR_FANOUT) for a, b in layout_payload])
|
||||
]
|
||||
|
||||
|
||||
# We use glbl_fine_ts_width in the output network so that collisions due
|
||||
# to insufficiently increasing timestamps are always reliably detected.
|
||||
# We can still have undetected collisions on the address by making it wrap
|
||||
# around, but those are more rare and easier to debug, and addresses are
|
||||
# not normally exposed directly to the ARTIQ user.
|
||||
def output_network_payload(channels, glbl_fine_ts_width):
|
||||
address_width = max(rtlink.get_address_width(channel.interface.o)
|
||||
for channel in channels)
|
||||
data_width = max(rtlink.get_data_width(channel.interface.o)
|
||||
for channel in channels)
|
||||
|
||||
layout = [("channel", bits_for(len(channels)-1))]
|
||||
if glbl_fine_ts_width:
|
||||
layout.append(("fine_ts", glbl_fine_ts_width))
|
||||
if address_width:
|
||||
layout.append(("address", address_width))
|
||||
if data_width:
|
||||
layout.append(("data", data_width))
|
||||
|
||||
return layout
|
||||
|
||||
|
||||
def output_network_node(seqn_width, layout_payload):
|
||||
return [
|
||||
("valid", 1),
|
||||
("seqn", seqn_width),
|
||||
("replace_occured", 1),
|
||||
("nondata_replace_occured", 1),
|
||||
("payload", layout_payload)
|
||||
]
|
||||
|
|
|
|||
|
|
@ -1,105 +1 @@
|
|||
from functools import reduce
|
||||
from operator import or_
|
||||
|
||||
from nmigen import *
|
||||
|
||||
from rtio.sed import layouts
|
||||
from rtio.sed.output_network import OutputNetwork
|
||||
|
||||
__all__ = ["OutputDriver"]
|
||||
|
||||
class OutputDriver(Elaboratable):
|
||||
def __init__(self, channels, glbl_fine_ts_width, lane_count, seqn_width):
|
||||
self.channels = channels
|
||||
self.glbl_fine_ts_width = glbl_fine_ts_width
|
||||
self.lane_count = lane_count
|
||||
self.seqn_width = seqn_width
|
||||
self.collision = Signal()
|
||||
self.collision_channel = Signal(range(len(channels)), reset_less=True)
|
||||
self.busy = Signal()
|
||||
self.busy_channel = Signal(range(len(channels)), reset_less=True)
|
||||
self.input = None
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
# output network
|
||||
layout_on_payload = layouts.output_network_payload(self.channels, self.glbl_fine_ts_width)
|
||||
output_network = OutputNetwork(self.lane_count, self.seqn_width, layout_on_payload)
|
||||
m.submodules.output_network = output_network
|
||||
self.input = output_network.input
|
||||
|
||||
# detect collisions (adds one pipeline stage)
|
||||
layout_lane_data = [
|
||||
("valid", 1),
|
||||
("collision", 1),
|
||||
("payload", layout_on_payload)
|
||||
]
|
||||
lane_datas = [Record(layout_lane_data, reset_less=True) for _ in range(lane_count)]
|
||||
en_replaces = [channel.interface.o.enable_replace for channel in channels]
|
||||
for lane_data, on_output in zip(lane_datas, output_network.output):
|
||||
lane_data.valid.reset_less = False
|
||||
lane_data.collision.reset_less = False
|
||||
replace_occurred_r = Signal()
|
||||
nondata_replace_occurred_r = Signal()
|
||||
m.d.sync += lane_data.valid.eq(on_output.valid)
|
||||
m.d.sync += lane_data.payload.eq(on_output.payload)
|
||||
m.d.sync += replace_occurred_r.eq(on_output.replace_occurred)
|
||||
m.d.sync += nondata_replace_occurred_r.eq(on_output.nondata_replace_occurred)
|
||||
|
||||
en_replaces_rom = Memory(1, len(en_replaces), init=en_replaces)
|
||||
en_replaces_rom_rdport = en_replaces_rom.read_port()
|
||||
m.submodules.en_replaces_rom_rdport = en_replaces_rom_rdport
|
||||
m.d.comb += en_replaces_rom_rdport.addr.eq(on_output.payload.channel)
|
||||
m.d.comb += lane_data.collision.eq(replace_occurred_r & (~en_replaces_rom_rdport.data | nondata_replace_occurred_r))
|
||||
|
||||
m.d.sync += self.collision.eq(0)
|
||||
m.d.sync += self.collision_channel.eq(0)
|
||||
for lane_data in lane_datas:
|
||||
with m.If(lane_data.valid & lane_data.collision):
|
||||
m.d.sync += self.collision.eq(1)
|
||||
m.d.sync += self.collision_channel.eq(lane_data.payload.channel)
|
||||
|
||||
# demultiplex channels (adds one pipeline stage)
|
||||
for n, channel in enumerate(channels):
|
||||
oif = channel.interface.o
|
||||
|
||||
onehot_stb = []
|
||||
onehot_fine_ts = []
|
||||
onehot_address = []
|
||||
onehot_data = []
|
||||
for lane_data in lane_datas:
|
||||
selected = Signal()
|
||||
m.d.comb += selected.eq(lane_data.valid & ~lane_data.collision & (lane_data.payload.channel == n))
|
||||
onehot_stb.append(selected)
|
||||
if hasattr(lane_data.payload, "fine_ts") and hasattr(oif, "fine_ts"):
|
||||
ts_shift = len(lane_data.payload.fine_ts) - len(oif.fine_ts)
|
||||
onehot_fine_ts.append(Mux(selected, lane_data.payload.fine_ts[ts_shift:], 0))
|
||||
if hasattr(lane_data.payload, "address"):
|
||||
onehot_address.append(Mux(selected, lane_data.payload.address, 0))
|
||||
if hasattr(lane_data.payload, "data"):
|
||||
onehot_data.append(Mux(selected, lane_data.payload.data, 0))
|
||||
|
||||
m.d.sync += oif.stb.eq(reduce(or_, onehot_stb))
|
||||
if hasattr(oif, "fine_ts"):
|
||||
m.d.sync += oif.fine_ts.eq(reduce(or_, onehot_fine_ts))
|
||||
if hasattr(oif, "address"):
|
||||
m.d.sync += oif.address.eq(reduce(or_, onehot_address))
|
||||
if hasattr(oif, "data"):
|
||||
m.d.sync += oif.data.eq(reduce(or_, onehot_data))
|
||||
|
||||
# detect busy errors, at lane level to reduce muxing
|
||||
m.d.sync += self.busy.eq(0)
|
||||
m.d.sync += self.busy_channel.eq(0)
|
||||
for lane_data in lane_datas:
|
||||
stb_r = Signal()
|
||||
channel_r = Signal(range(len(channels)), reset_less=True)
|
||||
m.d.sync += stb_r.eq(lane_data.valid & ~lane_data.collision)
|
||||
m.d.sync += channel_r.eq(lane_data.payload.channel)
|
||||
with m.If(stb_r & Array(channel.interface.o.busy for channel in channels)[channel_r]):
|
||||
m.d.sync += self.busy.eq(1)
|
||||
m.d.sync += self.busy_channel.eq(channel_r)
|
||||
|
||||
return m
|
||||
|
||||
OutputDriver([], 1, 1, 1).elaborate(None)
|
||||
|
|
|
|||
|
|
@ -1,105 +1 @@
|
|||
from nmigen import *
|
||||
from nmigen.utils import *
|
||||
|
||||
from rtio.sed import layouts
|
||||
|
||||
__all__ = ["latency", "OutputNetwork"]
|
||||
|
||||
# Based on: https://github.com/Bekbolatov/SortingNetworks/blob/master/src/main/js/gr.js
|
||||
def boms_get_partner(n, l, p):
|
||||
if p == 1:
|
||||
return n ^ (1 << (l - 1))
|
||||
scale = 1 << (l - p)
|
||||
box = 1 << p
|
||||
sn = n//scale - n//scale//box*box
|
||||
if sn == 0 or sn == (box - 1):
|
||||
return n
|
||||
if (sn % 2) == 0:
|
||||
return n - scale
|
||||
return n + scale
|
||||
|
||||
def boms_steps_pairs(lane_count):
|
||||
d = log2_int(lane_count)
|
||||
steps = []
|
||||
for l in range(1, d+1):
|
||||
for p in range(1, l+1):
|
||||
pairs = []
|
||||
for n in range(2**d):
|
||||
partner = boms_get_partner(n, l, p)
|
||||
if partner != n:
|
||||
if partner > n:
|
||||
pair = (n, partner)
|
||||
else:
|
||||
pair = (partner, n)
|
||||
if pair not in pairs:
|
||||
pairs.append(pair)
|
||||
steps.append(pairs)
|
||||
return steps
|
||||
|
||||
def latency(lane_count):
|
||||
d = log2_int(lane_count)
|
||||
return sum(l for l in range(1, d+1))
|
||||
|
||||
def cmp_wrap(a, b):
|
||||
return Mux((a[-2] == a[-1]) & (b[-2] == b[-1]) & (a[-1] != b[-1]), a[-1], a < b)
|
||||
|
||||
class OutputNetwork(Elaboratable):
|
||||
def __init__(self, lane_count, seqn_width, layout_payload):
|
||||
self.lane_count = lane_count
|
||||
self.seqn_width = seqn_width
|
||||
self.layout_payload = layout_payload
|
||||
self.input = [Record(layouts.output_network_node(seqn_width, layout_payload))
|
||||
for _ in range(lane_count)]
|
||||
self.output = None
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
step_input = self.input
|
||||
for step in boms_steps_pairs(self.lane_count):
|
||||
step_output = []
|
||||
for i in range(lane_count):
|
||||
rec = Record(layouts.output_network_node(seqn_width, layout_payload),
|
||||
reset_less=True)
|
||||
rec.valid.reset_less = False
|
||||
step_output.append(rec)
|
||||
|
||||
for node1, node2 in step:
|
||||
nondata_difference = Signal()
|
||||
for field, _ in layout_payload:
|
||||
if field != "data":
|
||||
f1 = getattr(step_input[node1].payload, field)
|
||||
f2 = getattr(step_input[node2].payload, field)
|
||||
with m.If(f1 != f2):
|
||||
m.d.comb += nondata_difference.eq(1)
|
||||
|
||||
k1 = Cat(step_input[node1].payload.channel, ~step_input[node1].valid)
|
||||
k2 = Cat(step_input[node2].payload.channel, ~step_input[node2].valid)
|
||||
with m.If(k1 == k2):
|
||||
with m.If(cmp_wrap(step_input[node1].seqn, step_input[node2].seqn)):
|
||||
m.d.sync += step_output[node1].eq(step_input[node2])
|
||||
m.d.sync += step_output[node2].eq(step_input[node1])
|
||||
with m.Else():
|
||||
m.d.sync += step_output[node1].eq(step_input[node1])
|
||||
m.d.sync += step_output[node2].eq(step_input[node2])
|
||||
m.d.sync += step_output[node1].replace_occurred.eq(1)
|
||||
m.d.sync += step_output[node1].nondata_replace_occurred.eq(nondata_difference),
|
||||
m.d.sync += step_output[node2].valid.eq(0)
|
||||
with m.Elif(k1 < k2):
|
||||
m.d.sync += step_output[node1].eq(step_input[node1])
|
||||
m.d.sync += step_output[node2].eq(step_input[node2])
|
||||
with m.Else():
|
||||
m.d.sync += step_output[node1].eq(step_input[node2])
|
||||
m.d.sync += step_output[node2].eq(step_input[node1])
|
||||
|
||||
unchanged = list(range(lane_count))
|
||||
for node1, node2 in step:
|
||||
unchanged.remove(node1)
|
||||
unchanged.remove(node2)
|
||||
for node in unchanged:
|
||||
m.d.sync += step_output[node].eq(step_input[node])
|
||||
|
||||
self.output = step_output
|
||||
step_input = step_output
|
||||
|
||||
return m
|
||||
|
|
|
|||
Loading…
Reference in New Issue