Restructure rtio.cri to follow nMigen convention
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@ -31,8 +31,8 @@ $ python -m rtio.test.sed.output_network
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- - [ ] `rtio.rtlink`
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- - [x] `rtio.sed.output_network` - Sorting network (high priority)
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- - [ ] `rtio.sed.output_driver`
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- [ ] Restructure to code to follow nMigen convention and re-validate existing assertions
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- - [ ] `rtio.cri` (`Interface` and `CRIDecoder` only)
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- [ ] Restructure to code to follow nMigen convention and re-validate existing assertions (if any)
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- - [x] `rtio.cri` (`Interface` and `CRIDecoder` only)
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- - [ ] `rtio.rtlink`
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- - [x] `rtio.sed.output_network`
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- - [ ] `rtio.sed.output_driver`
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15
rtio/cri.py
15
rtio/cri.py
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@ -59,16 +59,22 @@ class Interface(Record):
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class CRIDecoder(Elaboratable):
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def __init__(self, slaves=2, master=None, mode="async", enable_routing=False):
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m = Module()
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self.m = m
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if isinstance(slaves, int):
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slaves = [Interface() for _ in range(slaves)]
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if master is None:
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master = Interface()
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self.slaves = slaves
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self.master = master
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self.mode = mode
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self.enable_routing = enable_routing
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# # #
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def elaborate(self, platform):
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m = Module()
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slaves = self.slaves
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master = self.master
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mode = self.mode
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enable_routing = self.enable_routing
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# routing
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if enable_routing:
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@ -114,8 +120,7 @@ class CRIDecoder(Elaboratable):
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if direction == DIR_FANIN:
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m.d.comb += getattr(master, name).eq(getattr(slave, name))
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def elaborate(self, platform):
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return self.m
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return m
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# Skip CRISwitch for now (depends on AutoCSR)
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