Refine assertions for case with replacements in sorting network
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@ -172,6 +172,8 @@ class OutputNetwork(Elaboratable):
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# - Not all outputs are valid
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# - All channel numbers in the input appear exactly once as a
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# valid output
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# - All valid outputs match an input modulo accounting
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# information
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with m.Else():
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m.d.comb += Assert(~channels_unique)
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all_valid = Signal(reset=1)
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@ -188,6 +190,19 @@ class OutputNetwork(Elaboratable):
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accum = accum & ((Past(input_node.payload.channel, clocks=network_latency) != self.output[node2].payload.channel) | ~self.output[node2].valid)
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input_channel_valid_once = input_channel_valid_once | accum
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m.d.comb += Assert(input_channel_valid_once)
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for output_node in self.output:
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with m.If(output_node.valid):
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found_input = Signal()
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for input_node in self.input:
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match = Signal(reset=1)
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with m.If(Past(input_node.seqn, clocks=network_latency) != output_node.seqn):
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m.d.comb += match.eq(0)
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for field, _ in layout_payload:
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with m.If(Past(getattr(input_node.payload, field), clocks=network_latency) != getattr(output_node.payload, field)):
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m.d.comb += match.eq(0)
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with m.If(match):
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m.d.comb += found_input.eq(1)
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m.d.comb += Assert(found_input)
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def elaborate(self, platform):
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return self.m
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