34 lines
1.0 KiB
Python
34 lines
1.0 KiB
Python
|
from nmigen.back.pysim import *
|
||
|
|
from ..cri import *
|
||
|
|
|
||
|
|
if __name__ == "__main__":
|
||
|
|
m = Module()
|
||
|
|
m.submodules.cri_decoder = cri_decoder = CRIDecoder()
|
||
|
|
|
||
|
|
sim = Simulator(m)
|
||
|
|
|
||
|
|
def process():
|
||
|
|
yield cri_decoder.master.cmd.eq(commands["write"])
|
||
|
|
yield cri_decoder.master.chan_sel.eq(0)
|
||
|
|
yield cri_decoder.master.o_timestamp.eq(0)
|
||
|
|
yield cri_decoder.master.o_data.eq(1)
|
||
|
|
yield cri_decoder.master.o_address.eq(0)
|
||
|
|
yield cri_decoder.master.i_timeout.eq(0)
|
||
|
|
yield
|
||
|
|
yield cri_decoder.master.cmd.eq(commands["write"])
|
||
|
|
yield cri_decoder.master.chan_sel.eq(0)
|
||
|
|
yield cri_decoder.master.o_timestamp.eq(1)
|
||
|
|
yield cri_decoder.master.o_data.eq(0)
|
||
|
|
yield cri_decoder.master.o_address.eq(0)
|
||
|
|
yield cri_decoder.master.i_timeout.eq(0)
|
||
|
|
yield
|
||
|
|
yield cri_decoder.master.cmd.eq(commands["nop"])
|
||
|
|
yield
|
||
|
|
|
||
|
|
sim.add_clock(1e-8)
|
||
|
|
sim.add_sync_process(process)
|
||
|
|
|
||
|
|
with sim.write_vcd('cri_decoder.vcd', 'cri_decoder.gtkw'):
|
||
|
|
sim.run()
|
||
|
|
|