31 lines
1.4 KiB
Python
31 lines
1.4 KiB
Python
from insn_SB_type import *
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class rvfi_insn_beq(rvfi_insn_SB_type):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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super(rvfi_insn_beq, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
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def ports(self):
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return super(rvfi_insn_beq, self).ports()
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def elaborate(self, platform):
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m = super(rvfi_insn_beq, self).elaborate(platform)
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# BEQ instruction
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cond = Signal(1)
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m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata)
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next_pc = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
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m.d.comb += self.spec_pc_wdata.eq(next_pc)
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m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
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# default assignments
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m.d.comb += self.spec_rd_addr.eq(0)
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m.d.comb += self.spec_rd_wdata.eq(0)
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m.d.comb += self.spec_mem_addr.eq(0)
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m.d.comb += self.spec_mem_rmask.eq(0)
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m.d.comb += self.spec_mem_wmask.eq(0)
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m.d.comb += self.spec_mem_wdata.eq(0)
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return m
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