riscv-formal-nmigen/rvfi/cores/minerva/memory_bus.py

43 lines
904 B
Python

from nmigen import *
"""
Memory Bus (Wishbone Slave)
"""
class MemoryBus(Elaboratable):
def __init__(self):
self.adr = Signal(30)
self.dat_w = Signal(32)
self.dat_r = Signal(32)
self.sel = Signal(4)
self.cyc = Signal(1)
self.stb = Signal(1)
self.ack = Signal(1)
self.we = Signal(1)
self.cti = Signal(3)
self.bte = Signal(2)
self.err = Signal(1)
def ports(self):
input_ports = [
self.adr,
self.dat_w,
self.sel,
self.cyc,
self.stb,
self.we,
self.cti,
self.bte
]
output_ports = [
self.dat_r,
self.ack,
self.err
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# TODO
return m