487 lines
21 KiB
Python
487 lines
21 KiB
Python
from nmigen.test.utils import *
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from ...checks.insn_check import *
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from ...checks.pc_fwd_check import *
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from ...checks.pc_bwd_check import *
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from ...checks.reg_check import *
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from ...checks.causal_check import *
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from ...checks.liveness_check import *
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from ...checks.unique_check import *
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from minerva.core import *
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from ...insns.insn_lui import *
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from ...insns.insn_auipc import *
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from ...insns.insn_jal import *
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from ...insns.insn_jalr import *
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from ...insns.insn_beq import *
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from ...insns.insn_bne import *
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from ...insns.insn_blt import *
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from ...insns.insn_bge import *
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from ...insns.insn_bltu import *
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from ...insns.insn_bgeu import *
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from ...insns.insn_lb import *
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from ...insns.insn_lh import *
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from ...insns.insn_lw import *
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from ...insns.insn_lbu import *
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from ...insns.insn_lhu import *
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from ...insns.insn_sb import *
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from ...insns.insn_sh import *
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from ...insns.insn_sw import *
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from ...insns.insn_addi import *
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from ...insns.insn_slti import *
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from ...insns.insn_sltiu import *
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from ...insns.insn_xori import *
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from ...insns.insn_ori import *
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from ...insns.insn_andi import *
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from ...insns.insn_slli import *
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from ...insns.insn_srli import *
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from ...insns.insn_srai import *
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from ...insns.insn_add import *
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from ...insns.insn_sub import *
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from ...insns.insn_sll import *
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from ...insns.insn_slt import *
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from ...insns.insn_sltu import *
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from ...insns.insn_xor import *
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from ...insns.insn_srl import *
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from ...insns.insn_sra import *
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from ...insns.insn_or import *
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from ...insns.insn_and import *
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from ...insns.insn_mul import *
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from ...insns.insn_mulh import *
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from ...insns.insn_mulhsu import *
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from ...insns.insn_mulhu import *
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from ...insns.insn_div import *
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from ...insns.insn_divu import *
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from ...insns.insn_rem import *
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from ...insns.insn_remu import *
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from collections import namedtuple
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RISCVFormalParameters = namedtuple('RISCVFormalParameters',
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['ilen', 'xlen', 'csr_misa', 'compressed', 'aligned_mem', 'altops'])
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class InsnSpec(Elaboratable):
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def __init__(self, insn_model):
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self.insn_model = insn_model
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.insn_spec = insn_spec = InsnCheck(
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params=RISCVFormalParameters(32, 32, False, False, False, True),
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insn_model=self.insn_model,
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rvformal_addr_valid=lambda x:Const(1))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
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m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(AnySeq(1))
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(AnySeq(1))
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m.d.comb += insn_spec.reset.eq(AnySeq(1))
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m.d.comb += insn_spec.check.eq(AnySeq(1))
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m.d.comb += insn_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += insn_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += insn_spec.rvfi_insn.eq(cpu.rvfi.insn)
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m.d.comb += insn_spec.rvfi_trap.eq(cpu.rvfi.trap)
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m.d.comb += insn_spec.rvfi_halt.eq(cpu.rvfi.halt)
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m.d.comb += insn_spec.rvfi_intr.eq(cpu.rvfi.intr)
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m.d.comb += insn_spec.rvfi_mode.eq(cpu.rvfi.mode)
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m.d.comb += insn_spec.rvfi_ixl.eq(cpu.rvfi.ixl)
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m.d.comb += insn_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += insn_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += insn_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += insn_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += insn_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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m.d.comb += insn_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += insn_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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m.d.comb += insn_spec.rvfi_mem_addr.eq(cpu.rvfi.mem_addr)
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m.d.comb += insn_spec.rvfi_mem_rmask.eq(cpu.rvfi.mem_rmask)
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m.d.comb += insn_spec.rvfi_mem_wmask.eq(cpu.rvfi.mem_wmask)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(cpu.rvfi.mem_rdata)
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m.d.comb += insn_spec.rvfi_mem_wdata.eq(cpu.rvfi.mem_wdata)
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return m
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class InsnTestCase(FHDLTestCase):
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def verify(self):
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print("Verifying LUI instruction ...")
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self.assertFormal(InsnSpec(InsnLui), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnLui), mode="bmc", depth=40)
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print("Verifying AUIPC instruction ...")
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self.assertFormal(InsnSpec(InsnAuipc), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnAuipc), mode="bmc", depth=40)
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print("Verifying JAL instruction ...")
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self.assertFormal(InsnSpec(InsnJal), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnJal), mode="bmc", depth=40)
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print("Verifying JALR instruction ...")
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self.assertFormal(InsnSpec(InsnJalr), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnJalr), mode="bmc", depth=40)
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print("Verifying BEQ instruction ...")
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self.assertFormal(InsnSpec(InsnBeq), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnBeq), mode="bmc", depth=40)
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print("Verifying BNE instruction ...")
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self.assertFormal(InsnSpec(InsnBne), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnBne), mode="bmc", depth=40)
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print("Verifying BLT instruction ...")
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self.assertFormal(InsnSpec(InsnBlt), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnBlt), mode="bmc", depth=40)
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print("Verifying BGE instruction ...")
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self.assertFormal(InsnSpec(InsnBge), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnBge), mode="bmc", depth=40)
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print("Verifying BLTU instruction ...")
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self.assertFormal(InsnSpec(InsnBltu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnBltu), mode="bmc", depth=40)
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print("Verifying BGEU instruction ...")
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self.assertFormal(InsnSpec(InsnBgeu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnBgeu), mode="bmc", depth=40)
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print("Verifying LB instruction ...")
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self.assertFormal(InsnSpec(InsnLb), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnLb), mode="bmc", depth=40)
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print("Verifying LH instruction ...")
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self.assertFormal(InsnSpec(InsnLh), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnLh), mode="bmc", depth=40)
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print("Verifying LW instruction ...")
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self.assertFormal(InsnSpec(InsnLw), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnLw), mode="bmc", depth=40)
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print("Verifying LBU instruction ...")
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self.assertFormal(InsnSpec(InsnLbu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnLbu), mode="bmc", depth=40)
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print("Verifying LHU instruction ...")
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self.assertFormal(InsnSpec(InsnLhu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnLhu), mode="bmc", depth=40)
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print("Verifying SB instruction ...")
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self.assertFormal(InsnSpec(InsnSb), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSb), mode="bmc", depth=40)
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print("Verifying SH instruction ...")
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self.assertFormal(InsnSpec(InsnSh), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSh), mode="bmc", depth=40)
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print("Verifying SW instruction ...")
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self.assertFormal(InsnSpec(InsnSw), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSw), mode="bmc", depth=40)
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print("Verifying ADDI instruction ...")
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self.assertFormal(InsnSpec(InsnAddi), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnAddi), mode="bmc", depth=40)
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print("Verifying SLTI instruction ...")
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self.assertFormal(InsnSpec(InsnSlti), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSlti), mode="bmc", depth=40)
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print("Verifying SLTIU instruction ...")
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self.assertFormal(InsnSpec(InsnSltiu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSltiu), mode="bmc", depth=40)
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print("Verifying XORI instruction ...")
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self.assertFormal(InsnSpec(InsnXori), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnXori), mode="bmc", depth=40)
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print("Verifying ORI instruction ...")
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self.assertFormal(InsnSpec(InsnOri), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnOri), mode="bmc", depth=40)
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print("Verifying ANDI instruction ...")
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self.assertFormal(InsnSpec(InsnAndi), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnAndi), mode="bmc", depth=40)
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print("Verifying SLLI instruction ...")
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self.assertFormal(InsnSpec(InsnSlli), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSlli), mode="bmc", depth=40)
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print("Verifying SRLI instruction ...")
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self.assertFormal(InsnSpec(InsnSrli), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSrli), mode="bmc", depth=40)
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print("Verifying SRAI instruction ...")
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self.assertFormal(InsnSpec(InsnSrai), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSrai), mode="bmc", depth=40)
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print("Verifying ADD instruction ...")
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self.assertFormal(InsnSpec(InsnAdd), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnAdd), mode="bmc", depth=40)
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print("Verifying SUB instruction ...")
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self.assertFormal(InsnSpec(InsnSub), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSub), mode="bmc", depth=40)
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print("Verifying SLL instruction ...")
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self.assertFormal(InsnSpec(InsnSll), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSll), mode="bmc", depth=40)
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print("Verifying SLT instruction ...")
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self.assertFormal(InsnSpec(InsnSlt), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSlt), mode="bmc", depth=40)
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print("Verifying SLTU instruction ...")
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self.assertFormal(InsnSpec(InsnSltu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSltu), mode="bmc", depth=40)
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print("Verifying XOR instruction ...")
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self.assertFormal(InsnSpec(InsnXor), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnXor), mode="bmc", depth=40)
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print("Verifying SRL instruction ...")
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self.assertFormal(InsnSpec(InsnSrl), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSrl), mode="bmc", depth=40)
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print("Verifying SRA instruction ...")
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self.assertFormal(InsnSpec(InsnSra), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnSra), mode="bmc", depth=40)
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print("Verifying OR instruction ...")
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self.assertFormal(InsnSpec(InsnOr), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnOr), mode="bmc", depth=40)
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print("Verifying AND instruction ...")
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self.assertFormal(InsnSpec(InsnAnd), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnAnd), mode="bmc", depth=40)
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print("Verifying MUL instruction ...")
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self.assertFormal(InsnSpec(InsnMul), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnMul), mode="bmc", depth=40)
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print("Verifying MULH instruction ...")
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self.assertFormal(InsnSpec(InsnMulh), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnMulh), mode="bmc", depth=40)
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print("Verifying MULHSU instruction ...")
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self.assertFormal(InsnSpec(InsnMulhsu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnMulhsu), mode="bmc", depth=40)
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print("Verifying MULHU instruction ...")
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self.assertFormal(InsnSpec(InsnMulhu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnMulhu), mode="bmc", depth=40)
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print("Verifying DIV instruction ...")
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self.assertFormal(InsnSpec(InsnDiv), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnDiv), mode="bmc", depth=40)
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print("Verifying DIVU instruction ...")
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self.assertFormal(InsnSpec(InsnDivu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnDivu), mode="bmc", depth=40)
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print("Verifying REM instruction ...")
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self.assertFormal(InsnSpec(InsnRem), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnRem), mode="bmc", depth=40)
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print("Verifying REMU instruction ...")
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self.assertFormal(InsnSpec(InsnRemu), mode="cover", depth=40)
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self.assertFormal(InsnSpec(InsnRemu), mode="bmc", depth=40)
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class PcFwdSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.pc_fwd_spec = pc_fwd_spec = PcFwdCheck(
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params=RISCVFormalParameters(32, 32, False, False, False, True),
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rvformal_addr_valid=lambda x:Const(1))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
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m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(AnySeq(1))
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(AnySeq(1))
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m.d.comb += pc_fwd_spec.reset.eq(AnySeq(1))
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m.d.comb += pc_fwd_spec.check.eq(AnySeq(1))
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m.d.comb += pc_fwd_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += pc_fwd_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += pc_fwd_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += pc_fwd_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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return m
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class PcFwdTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(PcFwdSpec(), mode="cover", depth=40)
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self.assertFormal(PcFwdSpec(), mode="bmc", depth=40)
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class PcBwdSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.pc_bwd_spec = pc_bwd_spec = PcBwdCheck(
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params=RISCVFormalParameters(32, 32, False, False, False, True),
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rvformal_addr_valid=lambda x:Const(1))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
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m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(AnySeq(1))
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(AnySeq(1))
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m.d.comb += pc_bwd_spec.reset.eq(AnySeq(1))
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m.d.comb += pc_bwd_spec.check.eq(AnySeq(1))
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m.d.comb += pc_bwd_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += pc_bwd_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += pc_bwd_spec.rvfi_pc_rdata.eq(cpu.rvfi.pc_rdata)
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m.d.comb += pc_bwd_spec.rvfi_pc_wdata.eq(cpu.rvfi.pc_wdata)
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return m
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class PcBwdTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(PcBwdSpec(), mode="cover", depth=40)
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self.assertFormal(PcBwdSpec(), mode="bmc", depth=40)
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class RegSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.reg_spec = reg_spec = RegCheck(params=RISCVFormalParameters(32, 32, False, False, False, True))
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# Wire input ports to Minerva core
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m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
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m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
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m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
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m.d.comb += cpu.ibus.err.eq(AnySeq(1))
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m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
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m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
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m.d.comb += cpu.dbus.err.eq(AnySeq(1))
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m.d.comb += reg_spec.reset.eq(AnySeq(1))
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m.d.comb += reg_spec.check.eq(AnySeq(1))
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m.d.comb += reg_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += reg_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += reg_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += reg_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
|
|
m.d.comb += reg_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
m.d.comb += reg_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
|
|
m.d.comb += reg_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += reg_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
|
|
|
|
return m
|
|
|
|
class RegTestCase(FHDLTestCase):
|
|
def verify(self):
|
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self.assertFormal(RegSpec(), mode="cover", depth=40)
|
|
self.assertFormal(RegSpec(), mode="bmc", depth=40)
|
|
|
|
class CausalSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.causal_spec = causal_spec = CausalCheck()
|
|
|
|
# Wire input ports to Minerva core
|
|
m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
|
|
m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
|
|
m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.err.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.err.eq(AnySeq(1))
|
|
|
|
m.d.comb += causal_spec.reset.eq(AnySeq(1))
|
|
m.d.comb += causal_spec.check.eq(AnySeq(1))
|
|
|
|
m.d.comb += causal_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += causal_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
|
|
m.d.comb += causal_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += causal_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
|
|
m.d.comb += causal_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
|
|
|
|
return m
|
|
|
|
class CausalTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(CausalSpec(), mode="cover", depth=40)
|
|
self.assertFormal(CausalSpec(), mode="bmc", depth=40)
|
|
|
|
class LivenessSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.liveness_spec = liveness_spec = LivenessCheck()
|
|
|
|
# Wire input ports to Minerva core
|
|
m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
|
|
m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
|
|
m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.err.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.err.eq(AnySeq(1))
|
|
|
|
m.d.comb += liveness_spec.reset.eq(AnySeq(1))
|
|
m.d.comb += liveness_spec.trig.eq(AnySeq(1))
|
|
m.d.comb ++ liveness_spec.check.eq(AnySeq(1))
|
|
|
|
m.d.comb += liveness_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += liveness_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
m.d.comb += liveness_spec.rvfi_halt.eq(cpu.rvfi.halt)
|
|
|
|
return m
|
|
|
|
class LivenessTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(LivenessSpec(), mode="cover", depth=40)
|
|
self.assertFormal(LivenessSpec(), mode="bmc", depth=40)
|
|
|
|
class UniqueSpec(Elaboratable):
|
|
def elaborate(self, platform):
|
|
m = Module()
|
|
|
|
m.submodules.cpu = cpu = Minerva(with_rvfi=True)
|
|
m.submodules.unique_spec = unique_spec = UniqueCheck()
|
|
|
|
# Wire input ports to Minerva core
|
|
m.d.comb += cpu.external_interrupt.eq(AnySeq(32))
|
|
m.d.comb += cpu.timer_interrupt.eq(AnySeq(1))
|
|
m.d.comb += cpu.software_interrupt.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.ibus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.ibus.err.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.dat_r.eq(AnySeq(32))
|
|
m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
|
|
m.d.comb += cpu.dbus.err.eq(AnySeq(1))
|
|
|
|
m.d.comb += unique_spec.reset.eq(AnySeq(1))
|
|
m.d.comb += unique_spec.trig.eq(AnySeq(1))
|
|
m.d.comb += unique_spec.check.eq(AnySeq(1))
|
|
|
|
m.d.comb += unique_spec.rvfi_valid.eq(cpu.rvfi.valid)
|
|
m.d.comb += unique_spec.rvfi_order.eq(cpu.rvfi.order)
|
|
|
|
return m
|
|
|
|
class UniqueTestCase(FHDLTestCase):
|
|
def verify(self):
|
|
self.assertFormal(UniqueSpec(), mode="cover", depth=40)
|
|
self.assertFormal(UniqueSpec(), mode="bmc", depth=40)
|
|
|
|
print('*' * 80)
|
|
print('*' + ' ' * 78 + '*')
|
|
print('* Verifying the Minerva core ... *')
|
|
print('*' + ' ' * 78 + '*')
|
|
print('*' * 80)
|
|
|
|
print("Verifying RV32M instructions ...")
|
|
InsnTestCase().verify()
|
|
|
|
print("Verifying PC forward checks ...")
|
|
PcFwdTestCase().verify()
|
|
|
|
print("Verifying PC backward checks ...")
|
|
PcBwdTestCase().verify()
|
|
|
|
print("Verifying register checks ...")
|
|
RegTestCase().verify()
|
|
|
|
print("Verifying causal checks ...")
|
|
CausalTestCase().verify()
|
|
|
|
print("Verifying liveness checks ...")
|
|
LivenessTestCase().verify()
|
|
|
|
print("Verifying uniqueness checks ...")
|
|
UniqueTestCase().verify()
|
|
|
|
print('*' * 80)
|
|
print('*' + ' ' * 78 + '*')
|
|
print('* All verification tasks successful! *')
|
|
print('*' + ' ' * 78 + '*')
|
|
print('*' * 80)
|