29 lines
1.3 KiB
Python
29 lines
1.3 KiB
Python
from insn_I_type import *
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class rvfi_insn_jalr(rvfi_insn_I_type):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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super(rvfi_insn_jalr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
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def ports(self):
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return super(rvfi_insn_jalr, self).ports()
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def elaborate(self, platform):
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m = super(rvfi_insn_jalr, self).elaborate(platform)
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# JALR instruction
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next_pc = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN))
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111))
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m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
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m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
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m.d.comb += self.spec_pc_wdata.eq(next_pc)
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m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
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# default assignments
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m.d.comb += self.spec_rs2_addr.eq(0)
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m.d.comb += self.spec_mem_addr.eq(0)
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m.d.comb += self.spec_mem_rmask.eq(0)
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m.d.comb += self.spec_mem_wmask.eq(0)
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m.d.comb += self.spec_mem_wdata.eq(0)
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return m
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