Donald Sebastian Leung 7e8ca12e5f | ||
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.. | ||
Insn.py | ||
InsnAdd.py | ||
InsnAddi.py | ||
InsnAnd.py | ||
InsnAndi.py | ||
InsnAuipc.py | ||
InsnBeq.py | ||
InsnBge.py | ||
InsnBgeu.py | ||
InsnBlt.py | ||
InsnBltu.py | ||
InsnBne.py | ||
InsnJal.py | ||
InsnJalr.py | ||
InsnLb.py | ||
InsnLbu.py | ||
InsnLh.py | ||
InsnLhu.py | ||
InsnLui.py | ||
InsnLw.py | ||
InsnOr.py | ||
InsnOri.py | ||
InsnRV32IIType.py | ||
InsnRV32IITypeArith.py | ||
InsnRV32IITypeLoad.py | ||
InsnRV32IITypeShift.py | ||
InsnRV32IRType.py | ||
InsnRV32ISBType.py | ||
InsnRV32ISType.py | ||
InsnRV32IUType.py | ||
InsnSb.py | ||
InsnSh.py | ||
InsnSll.py | ||
InsnSlli.py | ||
InsnSlt.py | ||
InsnSlti.py | ||
InsnSltiu.py | ||
InsnSltu.py | ||
InsnSra.py | ||
InsnSrai.py | ||
InsnSrl.py | ||
InsnSrli.py | ||
InsnSub.py | ||
InsnSw.py | ||
InsnXor.py | ||
InsnXori.py | ||
README.md |
README.md
RISC-V Instructions
Instructions
Below is a table of RISC-V instructions supported by the original riscv-formal framework at the time of writing, categorized by instruction type.
Instruction type | Instructions |
---|---|
R-type | ADD, ADDW, AND, DIV, DIVU, DIVUW, DIVW, MUL, MULH, MULHSU, MULHU, MULW, OR, REM, REMU, REMUW, REMW, SLL, SLLW, SLT, SLTU, SRA, SRAW, SRL, SRLW, SUB, SUBW, XOR |
I-type | ADDI, ADDIW, ANDI, JALR, LB, LBU, LD, LH, LHU, LW, LWU, ORI, SLTI, SLTIU, XORI |
I-type (shift variation) | SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW |
S-type | SB, SD, SH, SW |
SB-type | BEQ, BGE, BGEU, BLT, BLTU, BNE |
U-type | AUIPC, LUI |
UJ-type | JAL |
CI-type | C_ADD, C_ADDI, C_ADDIW, C_JALR, C_JR, C_LI, C_MV |
CI-type (SP variation) | C_ADDI16SP |
CI-type (ANDI variation) | C_ANDI |
CI-type (LSP variation, 32 bit version) | C_LWSP |
CI-type (LSP variation, 64 bit version) | C_LDSP |
CI-type (LUI variation) | C_LUI |
CI-type (SLI variation) | C_SLLI |
CI-type (SRI variation) | C_SRAI, C_SRLI |
CIW-type | C_ADDI4SPN |
CS-type (ALU version) | C_ADDW, C_AND, C_OR, C_SUB, C_SUBW, C_XOR |
CS-type (32 bit version) | C_SW |
CS-type (64 bit version) | C_SD |
CSS-type (32 bit version) | C_SWSP |
CSS-type (64 bit version) | C_SDSP |
CB-type | C_BEQZ, C_BNEZ |
CJ-type | C_J, C_JAL |
CL-type (32 bit version) | C_LW |
CL-type (64 bit version) | C_LD |
Class Synopsis
Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions.
Insn
: General RISC-V instructionInsnRV32IRType
: RV32I R-Type InstructionInsnAdd
: ADD instructionInsnSub
: SUB instructionInsnSll
: SLL instructionInsnSlt
: SLT instructionInsnSltu
: SLTU instructionInsnXor
: XOR instructionInsnSrl
: SRL instructionInsnSra
: SRA instructionInsnOr
: OR instructionInsnAnd
: AND instruction
InsnRV32IITypeShift
: RV32I I-Type Instruction (Shift Variation)InsnSlli
: SLLI instructionInsnSrli
: SRLI instructionInsnSrai
: SRAI instruction
InsnRV32IIType
: RV32I I-Type InstructionInsnJalr
: JALR instructionInsnRV32IITypeLoad
: RV32I I-Type Instruction (Load Variation)InsnLb
: LB instructionInsnLh
: LH instructionInsnLw
: LW instructionInsnLbu
: LBU instructionInsnLhu
: LHU instruction
InsnRV32IITypeArith
: RV32I I-Type Instruction (Arithmetic Variation)InsnAddi
: ADDI instructionInsnSlti
: SLTI instructionInsnSltiu
: SLTIU instructionInsnXori
: XORI instructionInsnOri
: ORI instructionInsnAndi
: ANDI instruction
InsnRV32ISType
: RV32I S-Type InstructionInsnSb
: SB instructionInsnSh
: SH instructionInsnSw
: SW instruction
InsnRV32ISBType
: RV32I SB-Type InstructionInsnBeq
: BEQ instructionInsnBne
: BNE instructionInsnBlt
: BLT instructionInsnBge
: BGE instructionInsnBltu
: BLTU instructionInsnBgeu
: BGEU instruction
InsnJal
: JAL instructionInsnRV32IUType
: RV32I U-Type InstructionInsnLui
: LUI instructionInsnAuipc
: AUIPC instruction
Parameters
TODO