232 lines
7.6 KiB
Python
232 lines
7.6 KiB
Python
from nmigen import *
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from nmigen.utils import log2_int
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from ..cache import *
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from ..wishbone import *
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__all__ = ["PCSelector", "FetchUnitInterface", "BareFetchUnit", "CachedFetchUnit"]
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class PCSelector(Elaboratable):
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def __init__(self):
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self.f_pc = Signal(32)
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self.d_pc = Signal(32)
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self.d_branch_predict_taken = Signal()
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self.d_branch_target = Signal(32)
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self.d_valid = Signal()
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self.x_pc = Signal(32)
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self.x_fence_i = Signal()
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self.x_valid = Signal()
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self.m_branch_predict_taken = Signal()
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self.m_branch_taken = Signal()
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self.m_branch_target = Signal(32)
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self.m_exception = Signal()
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self.m_mret = Signal()
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self.m_valid = Signal()
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self.mtvec_r_base = Signal(30)
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self.mepc_r_base = Signal(30)
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self.a_pc = Signal(32)
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def elaborate(self, platform):
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m = Module()
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m_sel = Signal(reset=1)
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m_a_pc = Signal(32)
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with m.If(self.m_exception):
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m.d.comb += m_a_pc[2:].eq(self.mtvec_r_base)
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with m.Elif(self.m_mret):
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m.d.comb += m_a_pc[2:].eq(self.mepc_r_base)
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with m.Elif(self.m_branch_predict_taken & ~self.m_branch_taken):
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m.d.comb += m_a_pc[2:].eq(self.x_pc[2:])
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with m.Elif(~self.m_branch_predict_taken & self.m_branch_taken):
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m.d.comb += m_a_pc[2:].eq(self.m_branch_target[2:]),
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with m.Else():
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m.d.comb += m_sel.eq(0)
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with m.If(m_sel & self.m_valid):
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m.d.comb += self.a_pc[2:].eq(m_a_pc[2:])
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with m.Elif(self.x_fence_i & self.x_valid):
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m.d.comb += self.a_pc[2:].eq(self.d_pc[2:])
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with m.Elif(self.d_branch_predict_taken & self.d_valid):
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m.d.comb += self.a_pc[2:].eq(self.d_branch_target[2:]),
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with m.Else():
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m.d.comb += self.a_pc[2:].eq(self.f_pc[2:] + 1)
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return m
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class FetchUnitInterface:
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def __init__(self):
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self.ibus = Record(wishbone_layout)
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self.a_pc = Signal(32)
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self.a_stall = Signal()
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self.a_valid = Signal()
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self.f_stall = Signal()
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self.f_valid = Signal()
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self.a_busy = Signal()
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self.f_busy = Signal()
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self.f_instruction = Signal(32, reset=0x00000013) # nop (addi x0, x0, 0)
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self.f_fetch_error = Signal()
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self.f_badaddr = Signal(30)
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class BareFetchUnit(FetchUnitInterface, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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ibus_rdata = Signal.like(self.ibus.dat_r)
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with m.If(self.ibus.cyc):
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with m.If(self.ibus.ack | self.ibus.err | ~self.f_valid):
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m.d.sync += [
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self.ibus.cyc.eq(0),
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self.ibus.stb.eq(0),
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ibus_rdata.eq(self.ibus.dat_r)
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]
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with m.Elif(self.a_valid & ~self.a_stall):
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m.d.sync += [
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self.ibus.adr.eq(self.a_pc[2:]),
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self.ibus.cyc.eq(1),
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self.ibus.stb.eq(1)
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]
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m.d.comb += self.ibus.sel.eq(0b1111)
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with m.If(self.ibus.cyc & self.ibus.err):
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m.d.sync += [
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self.f_fetch_error.eq(1),
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self.f_badaddr.eq(self.ibus.adr)
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]
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with m.Elif(~self.f_stall):
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m.d.sync += self.f_fetch_error.eq(0)
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m.d.comb += self.a_busy.eq(self.ibus.cyc)
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with m.If(self.f_fetch_error):
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m.d.comb += self.f_busy.eq(0)
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with m.Else():
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m.d.comb += [
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self.f_busy.eq(self.ibus.cyc),
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self.f_instruction.eq(ibus_rdata)
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]
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return m
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class CachedFetchUnit(FetchUnitInterface, Elaboratable):
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def __init__(self, *icache_args):
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super().__init__()
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self.icache_args = icache_args
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self.f_pc = Signal(32)
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self.a_flush = Signal()
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def elaborate(self, platform):
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m = Module()
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icache = m.submodules.icache = L1Cache(*self.icache_args)
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a_icache_select = Signal()
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# Test whether the target address is inside the L1 cache region. We use bit masks in order
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# to avoid carry chains from arithmetic comparisons. This restricts the region boundaries
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# to powers of 2.
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with m.Switch(self.a_pc[2:]):
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def addr_below(limit):
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assert limit in range(1, 2**30 + 1)
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range_bits = log2_int(limit)
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const_bits = 30 - range_bits
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return "{}{}".format("0" * const_bits, "-" * range_bits)
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if icache.base >= 4:
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with m.Case(addr_below(icache.base >> 2)):
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m.d.comb += a_icache_select.eq(0)
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with m.Case(addr_below(icache.limit >> 2)):
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m.d.comb += a_icache_select.eq(1)
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with m.Default():
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m.d.comb += a_icache_select.eq(0)
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f_icache_select = Signal()
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f_flush = Signal()
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with m.If(~self.a_stall):
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m.d.sync += [
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f_icache_select.eq(a_icache_select),
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f_flush.eq(self.a_flush),
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]
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m.d.comb += [
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icache.s1_addr.eq(self.a_pc[2:]),
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icache.s1_stall.eq(self.a_stall),
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icache.s1_valid.eq(self.a_valid),
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icache.s2_addr.eq(self.f_pc[2:]),
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icache.s2_re.eq(f_icache_select),
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icache.s2_evict.eq(Const(0)),
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icache.s2_flush.eq(f_flush),
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icache.s2_valid.eq(self.f_valid),
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]
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ibus_arbiter = m.submodules.ibus_arbiter = WishboneArbiter()
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m.d.comb += ibus_arbiter.bus.connect(self.ibus)
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icache_port = ibus_arbiter.port(priority=0)
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m.d.comb += [
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icache_port.cyc.eq(icache.bus_re),
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icache_port.stb.eq(icache.bus_re),
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icache_port.adr.eq(icache.bus_addr),
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icache_port.sel.eq(0b1111),
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icache_port.cti.eq(Mux(icache.bus_last, Cycle.END, Cycle.INCREMENT)),
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icache_port.bte.eq(Const(log2_int(icache.nwords) - 1)),
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icache.bus_valid.eq(icache_port.ack),
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icache.bus_error.eq(icache_port.err),
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icache.bus_rdata.eq(icache_port.dat_r)
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]
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bare_port = ibus_arbiter.port(priority=1)
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bare_rdata = Signal.like(bare_port.dat_r)
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with m.If(bare_port.cyc):
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with m.If(bare_port.ack | bare_port.err | ~self.f_valid):
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m.d.sync += [
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bare_port.cyc.eq(0),
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bare_port.stb.eq(0),
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bare_rdata.eq(bare_port.dat_r)
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]
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with m.Elif(~a_icache_select & self.a_valid & ~self.a_stall):
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m.d.sync += [
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bare_port.cyc.eq(1),
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bare_port.stb.eq(1),
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bare_port.adr.eq(self.a_pc[2:])
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]
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m.d.comb += bare_port.sel.eq(0b1111)
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m.d.comb += self.a_busy.eq(bare_port.cyc)
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with m.If(self.ibus.cyc & self.ibus.err):
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m.d.sync += [
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self.f_fetch_error.eq(1),
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self.f_badaddr.eq(self.ibus.adr)
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]
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with m.Elif(~self.f_stall):
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m.d.sync += self.f_fetch_error.eq(0)
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with m.If(f_flush):
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m.d.comb += self.f_busy.eq(~icache.s2_flush_ack)
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with m.Elif(self.f_fetch_error):
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m.d.comb += self.f_busy.eq(0)
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with m.Elif(f_icache_select):
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m.d.comb += [
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self.f_busy.eq(icache.s2_miss),
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self.f_instruction.eq(icache.s2_rdata)
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]
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with m.Else():
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m.d.comb += [
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self.f_busy.eq(bare_port.cyc),
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self.f_instruction.eq(bare_rdata)
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]
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return m
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