22 lines
1.1 KiB
Python
22 lines
1.1 KiB
Python
from insn_I_type import *
|
|
|
|
class rvfi_insn_jalr(rvfi_insn_I_type):
|
|
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
|
|
super(rvfi_insn_jalr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
|
|
def ports(self):
|
|
return super(rvfi_insn_jalr, self).ports()
|
|
def elaborate(self, platform):
|
|
m = super(rvfi_insn_jalr, self).elaborate(platform)
|
|
|
|
# JALR instruction
|
|
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
|
m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN))
|
|
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111))
|
|
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
|
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
|
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
|
|
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
|
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
|
|
|
return m
|