145 lines
5.1 KiB
Python
145 lines
5.1 KiB
Python
from nmigen import *
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from ..isa import Funct3
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__all__ = ["DividerInterface", "Divider", "DummyDivider"]
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class DividerInterface:
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def __init__(self):
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self.x_op = Signal(3)
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self.x_src1 = Signal(32)
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self.x_src2 = Signal(32)
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self.x_valid = Signal()
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self.x_stall = Signal()
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self.m_result = Signal(32)
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self.m_busy = Signal()
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class Divider(DividerInterface, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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x_enable = Signal()
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x_modulus = Signal()
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x_signed = Signal()
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with m.Switch(self.x_op):
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with m.Case(Funct3.DIV):
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m.d.comb += x_enable.eq(1), x_signed.eq(1)
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with m.Case(Funct3.DIVU):
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m.d.comb += x_enable.eq(1)
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with m.Case(Funct3.REM):
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m.d.comb += x_enable.eq(1), x_modulus.eq(1), x_signed.eq(1)
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with m.Case(Funct3.REMU):
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m.d.comb += x_enable.eq(1), x_modulus.eq(1)
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x_negative = Signal()
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with m.If(x_modulus):
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m.d.comb += x_negative.eq(x_signed & self.x_src1[31])
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with m.Else():
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m.d.comb += x_negative.eq(x_signed & (self.x_src1[31] ^ self.x_src2[31]))
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x_dividend = Signal(32)
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x_divisor = Signal(32)
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m.d.comb += [
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x_dividend.eq(Mux(x_signed & self.x_src1[31], -self.x_src1, self.x_src1)),
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x_divisor.eq(Mux(x_signed & self.x_src2[31], -self.x_src2, self.x_src2))
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]
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m_modulus = Signal()
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m_negative = Signal()
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timer = Signal(range(33), reset=32)
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quotient = Signal(32)
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divisor = Signal(32)
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remainder = Signal(32)
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difference = Signal(33)
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with m.FSM() as fsm:
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with m.State("IDLE"):
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with m.If(x_enable & self.x_valid & ~self.x_stall):
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m.d.sync += [
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m_modulus.eq(x_modulus),
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m_negative.eq(x_negative)
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]
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with m.If(x_divisor == 0):
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# Division by zero
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m.d.sync += [
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quotient.eq(-1),
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remainder.eq(self.x_src1)
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]
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with m.Elif(x_signed & (self.x_src1 == -2**31) & (self.x_src2 == -1)):
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# Signed overflow
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m.d.sync += [
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quotient.eq(self.x_src1),
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remainder.eq(0)
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]
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with m.Elif(x_dividend == 0):
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m.d.sync += [
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quotient.eq(0),
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remainder.eq(0)
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]
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with m.Else():
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m.d.sync += [
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quotient.eq(x_dividend),
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remainder.eq(0),
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divisor.eq(x_divisor),
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timer.eq(timer.reset)
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]
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m.next = "DIVIDE"
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with m.State("DIVIDE"):
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m.d.comb += self.m_busy.eq(1)
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with m.If(timer != 0):
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m.d.sync += timer.eq(timer - 1)
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m.d.comb += difference.eq(Cat(quotient[31], remainder) - divisor)
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with m.If(difference[32]):
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m.d.sync += [
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remainder.eq(Cat(quotient[31], remainder)),
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quotient.eq(Cat(0, quotient))
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]
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with m.Else():
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m.d.sync += [
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remainder.eq(difference),
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quotient.eq(Cat(1, quotient))
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]
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with m.Else():
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m.d.sync += [
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quotient.eq(Mux(m_negative, -quotient, quotient)),
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remainder.eq(Mux(m_negative, -remainder, remainder))
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]
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m.next = "IDLE"
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m.d.comb += self.m_result.eq(Mux(m_modulus, remainder, quotient))
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return m
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class DummyDivider(DividerInterface, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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x_result = Signal.like(self.m_result)
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with m.Switch(self.x_op):
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# As per the RVFI specification (§ "Alternative Arithmetic Operations").
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# https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md
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with m.Case(Funct3.DIV):
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m.d.comb += x_result.eq((self.x_src1 - self.x_src2) ^ C(0x7f8529ec))
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with m.Case(Funct3.DIVU):
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m.d.comb += x_result.eq((self.x_src1 - self.x_src2) ^ C(0x10e8fd70))
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with m.Case(Funct3.REM):
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m.d.comb += x_result.eq((self.x_src1 - self.x_src2) ^ C(0x8da68fa5))
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with m.Case(Funct3.REMU):
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m.d.comb += x_result.eq((self.x_src1 - self.x_src2) ^ C(0x3138d0e1))
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with m.If(~self.x_stall):
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m.d.sync += self.m_result.eq(x_result)
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m.d.comb += self.m_busy.eq(C(0))
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return m
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