29 lines
1.1 KiB
Python
29 lines
1.1 KiB
Python
from nmigen import *
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from ..core import *
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from nmigen.test.utils import *
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from ....checks.reg_check import *
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class RegSpec(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = cpu = Minerva(with_rvfi=True)
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m.submodules.reg_spec = reg_spec = RegCheck(RISCV_FORMAL_XLEN=32)
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m.d.comb += reg_spec.reset.eq(0)
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m.d.comb += reg_spec.check.eq(1)
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m.d.comb += reg_spec.rvfi_valid.eq(cpu.rvfi.valid)
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m.d.comb += reg_spec.rvfi_order.eq(cpu.rvfi.order)
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m.d.comb += reg_spec.rvfi_rs1_addr.eq(cpu.rvfi.rs1_addr)
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m.d.comb += reg_spec.rvfi_rs1_rdata.eq(cpu.rvfi.rs1_rdata)
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m.d.comb += reg_spec.rvfi_rs2_addr.eq(cpu.rvfi.rs2_addr)
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m.d.comb += reg_spec.rvfi_rs2_rdata.eq(cpu.rvfi.rs2_rdata)
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m.d.comb += reg_spec.rvfi_rd_addr.eq(cpu.rvfi.rd_addr)
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m.d.comb += reg_spec.rvfi_rd_wdata.eq(cpu.rvfi.rd_wdata)
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return m
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class RegTestCase(FHDLTestCase):
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def verify(self):
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self.assertFormal(RegSpec(), mode="bmc", depth=12, engine="smtbmc --nopresat")
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