87 lines
3.4 KiB
Python
87 lines
3.4 KiB
Python
from nmigen import *
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class rvfi_insn_mul(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.rvfi_valid = Signal(1)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_valid = Signal(1)
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self.spec_trap = Signal(1)
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self.spec_rs1_addr = Signal(5)
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self.spec_rs2_addr = Signal(5)
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self.spec_rd_addr = Signal(5)
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self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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self.rvfi_insn,
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self.rvfi_pc_rdata,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_rdata,
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self.rvfi_mem_rdata
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]
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output_ports = [
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self.spec_valid,
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self.spec_trap,
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self.spec_rs1_addr,
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self.spec_rs2_addr,
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self.spec_rd_addr,
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self.spec_rd_wdata,
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self.spec_pc_wdata,
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self.spec_mem_addr,
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self.spec_mem_rmask,
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self.spec_mem_wmask,
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self.spec_mem_wdata
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]
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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# R-type instruction format (shift variation)
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insn_padding = Signal(self.RISCV_FORMAL_ILEN)
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m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
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insn_funct7 = Signal(7)
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m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
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insn_rs2 = Signal(5)
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m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
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insn_rs1 = Signal(5)
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m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
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insn_funct3 = Signal(3)
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m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
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insn_rd = Signal(5)
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m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
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insn_opcode = Signal(7)
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m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
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misa_ok = Signal(1)
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m.d.comb += misa_ok.eq(1)
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# MUL instruction
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result = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += result.eq(self.rvfi_rs1_rdata * self.rvfi_rs2_rdata)
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m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
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m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
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m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
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m.d.comb += self.spec_rd_addr.eq(insn_rd)
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
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m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
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# default assignments
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m.d.comb += self.spec_trap.eq(~misa_ok)
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m.d.comb += self.spec_mem_addr.eq(0)
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m.d.comb += self.spec_mem_rmask.eq(0)
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m.d.comb += self.spec_mem_wmask.eq(0)
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m.d.comb += self.spec_mem_wdata.eq(0)
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return m
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