65 lines
2.1 KiB
Python
65 lines
2.1 KiB
Python
from nmigen import *
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from nmigen.asserts import *
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"""
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Register Check
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"""
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class RegCheck(Elaboratable):
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def __init__(self, params):
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# Core-specific parameters
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self.params = params
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# Input ports
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self.reset = Signal(1)
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs1_rdata = Signal(self.params.xlen)
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self.rvfi_rs2_addr = Signal(5)
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self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_rd_addr = Signal(5)
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self.rvfi_rd_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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self.check,
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self.rvfi_valid,
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self.rvfi_order,
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self.rvfi_rs1_addr,
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self.rvfi_rs1_rdata,
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self.rvfi_rs2_addr,
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self.rvfi_rs2_rdata,
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self.rvfi_rd_addr,
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self.rvfi_rd_wdata
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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insn_order = AnyConst(64)
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register_index = AnyConst(5)
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register_shadow = Signal(self.params.xlen, reset=0)
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register_written = Signal(1, reset=0)
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with m.If(self.reset):
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m.d.sync += register_shadow.eq(0)
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m.d.sync += register_written.eq(0)
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with m.Else():
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with m.If(self.check):
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m.d.comb += Assume(self.rvfi_valid)
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m.d.comb += Assume(insn_order == self.rvfi_order)
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with m.If(register_written & (register_index == self.rvfi_rs1_addr)):
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m.d.comb += Assert(register_shadow == self.rvfi_rs1_rdata)
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with m.If(register_written & (register_index == self.rvfi_rs2_addr)):
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m.d.comb += Assert(register_shadow == self.rvfi_rs2_rdata)
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with m.Else():
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with m.If(self.rvfi_valid & (self.rvfi_order < insn_order) & (register_index == self.rvfi_rd_addr)):
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m.d.sync += register_shadow.eq(self.rvfi_rd_wdata)
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m.d.sync += register_written.eq(1)
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return m
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