Apply more PEP 8 guidelines, remove hacks and reduce code duplication #3
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@ -89,14 +89,14 @@ Below is a list of instructions currently supported by this port of the riscv-fo
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- `IsaRV32I`: RV32I Base ISA
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## Core-specific constants
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## Core-specific parameters
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The following core-specific constants are currently supported:
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The following core-specific parameters are currently supported:
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| Constant | Description | Valid value(s) | Supported by instruction(s) | Supported by ISA(s) |
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| --- | --- | --- | --- | --- |
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| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I |
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| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I |
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| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I |
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| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | RV32I |
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| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW | RV32I |
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| Constant | Description | Valid value(s) |
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| --- | --- | --- |
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| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` |
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| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` |
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| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` |
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| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` |
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| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` |
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@ -47,6 +47,7 @@ class Insn(Elaboratable):
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self.insn_opcode = Signal(7)
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self.misa_ok = Signal(1)
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self.ialign16 = Signal(1)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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@ -74,6 +75,7 @@ class Insn(Elaboratable):
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if self.params.csr_misa:
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output_ports.append(self.spec_csr_misa_rmask)
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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@ -7,6 +7,7 @@ ADD instruction
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class InsnAdd(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b000, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ ADDI instruction
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class InsnAddi(InsnRV32IITypeArith):
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def __init__(self, params):
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super().__init__(params, 0b000)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ AND instruction
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class InsnAnd(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b111, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ ANDI instruction
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class InsnAndi(InsnRV32IITypeArith):
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def __init__(self, params):
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super().__init__(params, 0b111)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ AUIPC instruction
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class InsnAuipc(InsnRV32IUType):
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def __init__(self, params):
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super().__init__(params, 0b0010111)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ BEQ instruction
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class InsnBeq(InsnRV32ISBType):
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def __init__(self, params):
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super().__init__(params, 0b000)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ BGE instruction
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class InsnBge(InsnRV32ISBType):
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def __init__(self, params):
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super().__init__(params, 0b101)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ BGEU instruction
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class InsnBgeu(InsnRV32ISBType):
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def __init__(self, params):
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super().__init__(params, 0b111)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ BLT instruction
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class InsnBlt(InsnRV32ISBType):
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def __init__(self, params):
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super().__init__(params, 0b100)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ BLTU instruction
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class InsnBltu(InsnRV32ISBType):
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def __init__(self, params):
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super().__init__(params, 0b110)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ BNE instruction
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class InsnBne(InsnRV32ISBType):
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def __init__(self, params):
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super().__init__(params, 0b001)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ LUI instruction
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class InsnLui(InsnRV32IUType):
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def __init__(self, params):
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super().__init__(params, 0b0110111)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ OR instruction
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class InsnOr(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b110, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ ORI instruction
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class InsnOri(InsnRV32IITypeArith):
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def __init__(self, params):
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super().__init__(params, 0b110)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -8,6 +8,7 @@ class InsnRV32IITypeArith(InsnRV32IIType):
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def __init__(self, params, funct3):
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super().__init__(params)
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self.funct3 = funct3
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -12,6 +12,7 @@ class InsnRV32IITypeLoad(InsnRV32IIType):
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self.is_signed = is_signed
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self.addr = Signal(self.params.xlen)
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self.result = Signal(8 * self.mask_shift)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -9,6 +9,7 @@ class InsnRV32IITypeShift(Insn):
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super().__init__(params)
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self.funct6 = funct6
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self.funct3 = funct3
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -10,6 +10,7 @@ class InsnRV32IRType(Insn):
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self.funct7 = funct7
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self.funct3 = funct3
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self.opcode = opcode
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -10,6 +10,7 @@ class InsnRV32ISType(Insn):
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self.funct3 = funct3
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self.mask_shift = mask_shift
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self.addr = Signal(self.params.xlen)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -8,6 +8,7 @@ class InsnRV32ISBType(Insn):
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def __init__(self, params, funct3):
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super().__init__(params)
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self.funct3 = funct3
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -8,6 +8,7 @@ class InsnRV32IUType(Insn):
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def __init__(self, params, opcode):
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super().__init__(params)
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self.opcode = opcode
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SLL instruction
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class InsnSll(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b001, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SLLI instruction
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class InsnSlli(InsnRV32IITypeShift):
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def __init__(self, params):
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super().__init__(params, 0b000000, 0b001)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SLT instruction
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class InsnSlt(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b010, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SLTI instruction
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class InsnSlti(InsnRV32IITypeArith):
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def __init__(self, params):
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super().__init__(params, 0b010)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SLTIU instruction
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class InsnSltiu(InsnRV32IITypeArith):
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def __init__(self, params):
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super().__init__(params, 0b011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SLTU instruction
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class InsnSltu(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b011, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SRA instruction
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class InsnSra(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0100000, 0b101, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SRAI instruction
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class InsnSrai(InsnRV32IITypeShift):
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def __init__(self, params):
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super().__init__(params, 0b010000, 0b101)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SRL instruction
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class InsnSrl(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b100, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SRLI instruction
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class InsnSrli(InsnRV32IITypeShift):
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def __init__(self, params):
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super().__init__(params, 0b000000, 0b101)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ SUB instruction
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class InsnSub(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0100000, 0b000, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ XOR instruction
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class InsnXor(InsnRV32IRType):
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def __init__(self, params):
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super().__init__(params, 0b0000000, 0b100, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -7,6 +7,7 @@ XORI instruction
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class InsnXori(InsnRV32IITypeArith):
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def __init__(self, params):
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super().__init__(params, 0b100)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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@ -41,38 +41,35 @@ RV32I Base ISA
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"""
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class IsaRV32I(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM):
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# Core-specific constants
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
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self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
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self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
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def __init__(self, params):
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# Core-specific parameters
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self.params = params
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# Input ports
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self.rvfi_valid = Signal(1)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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if self.RISCV_FORMAL_CSR_MISA:
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self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_insn = Signal(self.params.ilen)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_rs1_rdata = Signal(self.params.xlen)
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self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_mem_rdata = Signal(self.params.xlen)
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if self.params.csr_misa:
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self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
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# Output ports
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if self.RISCV_FORMAL_CSR_MISA:
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self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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if self.params.csr_misa:
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self.spec_csr_misa_rmask = Signal(self.params.xlen)
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self.spec_valid = Signal(1)
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self.spec_trap = Signal(1)
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self.spec_rs1_addr = Signal(5)
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self.spec_rs2_addr = Signal(5)
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self.spec_rd_addr = Signal(5)
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self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.spec_rd_wdata = Signal(self.params.xlen)
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self.spec_pc_wdata = Signal(self.params.xlen)
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self.spec_mem_addr = Signal(self.params.xlen)
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self.spec_mem_rmask = Signal(int(self.params.xlen // 8))
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self.spec_mem_wmask = Signal(int(self.params.xlen // 8))
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self.spec_mem_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.rvfi_valid,
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@ -82,7 +79,7 @@ class IsaRV32I(Elaboratable):
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self.rvfi_rs2_rdata,
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self.rvfi_mem_rdata
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]
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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input_ports.append(self.rvfi_csr_misa_rdata)
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output_ports = [
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self.spec_valid,
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@ -97,51 +94,52 @@ class IsaRV32I(Elaboratable):
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self.spec_mem_wmask,
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self.spec_mem_wdata
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]
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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output_ports.append(self.spec_csr_misa_rmask)
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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insn_submodules = {}
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m.submodules._lui = insn_submodules['lui'] = InsnLui(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
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m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._jal = insn_submodules['jal'] = InsnJal(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bne = insn_submodules['bne'] = InsnBne(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bge = insn_submodules['bge'] = InsnBge(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lb = insn_submodules['lb'] = InsnLb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lh = insn_submodules['lh'] = InsnLh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lw = insn_submodules['lw'] = InsnLw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._sb = insn_submodules['sb'] = InsnSb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._sw = insn_submodules['sw'] = InsnSw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._xori = insn_submodules['xori'] = InsnXori(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._ori = insn_submodules['ori'] = InsnOri(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._add = insn_submodules['add'] = InsnAdd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sub = insn_submodules['sub'] = InsnSub(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sll = insn_submodules['sll'] = InsnSll(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._xor = insn_submodules['xor'] = InsnXor(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sra = insn_submodules['sra'] = InsnSra(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._lui = insn_submodules['lui'] = InsnLui(self.params)
|
||||
m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.params)
|
||||
m.submodules._jal = insn_submodules['jal'] = InsnJal(self.params)
|
||||
m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.params)
|
||||
m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.params)
|
||||
m.submodules._bne = insn_submodules['bne'] = InsnBne(self.params)
|
||||
m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.params)
|
||||
m.submodules._bge = insn_submodules['bge'] = InsnBge(self.params)
|
||||
m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.params)
|
||||
m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.params)
|
||||
m.submodules._lb = insn_submodules['lb'] = InsnLb(self.params)
|
||||
m.submodules._lh = insn_submodules['lh'] = InsnLh(self.params)
|
||||
m.submodules._lw = insn_submodules['lw'] = InsnLw(self.params)
|
||||
m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.params)
|
||||
m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.params)
|
||||
m.submodules._sb = insn_submodules['sb'] = InsnSb(self.params)
|
||||
m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.params)
|
||||
m.submodules._sw = insn_submodules['sw'] = InsnSw(self.params)
|
||||
m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.params)
|
||||
m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.params)
|
||||
m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.params)
|
||||
m.submodules._xori = insn_submodules['xori'] = InsnXori(self.params)
|
||||
m.submodules._ori = insn_submodules['ori'] = InsnOri(self.params)
|
||||
m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.params)
|
||||
m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.params)
|
||||
m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.params)
|
||||
m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.params)
|
||||
m.submodules._add = insn_submodules['add'] = InsnAdd(self.params)
|
||||
m.submodules._sub = insn_submodules['sub'] = InsnSub(self.params)
|
||||
m.submodules._sll = insn_submodules['sll'] = InsnSll(self.params)
|
||||
m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.params)
|
||||
m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.params)
|
||||
m.submodules._xor = insn_submodules['xor'] = InsnXor(self.params)
|
||||
m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.params)
|
||||
m.submodules._sra = insn_submodules['sra'] = InsnSra(self.params)
|
||||
m.submodules._or = insn_submodules['or'] = InsnOr(self.params)
|
||||
m.submodules._and = insn_submodules['and'] = InsnAnd(self.params)
|
||||
|
||||
for _, insn in insn_submodules.items():
|
||||
m.d.comb += insn.rvfi_valid.eq(self.rvfi_valid)
|
||||
|
@ -150,7 +148,7 @@ class IsaRV32I(Elaboratable):
|
|||
m.d.comb += insn.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||||
m.d.comb += insn.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||||
m.d.comb += insn.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += insn.rvfi_csr_misa_rdata.eq(self.rvfi_csr_misa_rdata)
|
||||
|
||||
spec_valid = 0
|
||||
|
@ -208,7 +206,7 @@ class IsaRV32I(Elaboratable):
|
|||
spec_mem_wdata = Mux(insn.spec_valid, insn.spec_mem_wdata, spec_mem_wdata)
|
||||
m.d.comb += self.spec_mem_wdata.eq(spec_mem_wdata)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
spec_csr_misa_rmask = 0
|
||||
for _, insn in insn_submodules.items():
|
||||
spec_csr_misa_rmask = Mux(insn.spec_valid, insn.spec_csr_misa_rmask, spec_csr_misa_rmask)
|
||||
|
|
Loading…
Reference in New Issue