M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Refactor supported instructions to improve code reuse #1

Merged
dsleung merged 84 commits from feature/refactor-insns into master 2020-08-06 09:47:30 +08:00
Conversation 0 Commits 84 Files Changed 56 -3462
50 changed files with 0 additions and 3462 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit aa9967e83d - Show all commits

30
insns/insn_I_type.py
View File

@ -1,30 +0,0 @@
from insn_general import *
class rvfi_insn_I_type(rvfi_insn_general):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_I_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
self.insn_rs1 = Signal(5)
self.insn_funct3 = Signal(3)
self.insn_rd = Signal(5)
self.insn_opcode = Signal(7)
self.misa_ok = Signal(1)
self.ialign16 = Signal(1)
def ports(self):
return super(rvfi_insn_I_type, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_I_type, self).elaborate(platform)
# I-type instruction format
m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.ialign16.eq(0)
return m

30
insns/insn_SB_type.py
View File

@ -1,30 +0,0 @@
from insn_general import *
class rvfi_insn_SB_type(rvfi_insn_general):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_SB_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
self.insn_rs2 = Signal(5)
self.insn_rs1 = Signal(5)
self.insn_funct3 = Signal(3)
self.insn_opcode = Signal(7)
self.misa_ok = Signal(1)
self.ialign16 = Signal(1)
def ports(self):
return super(rvfi_insn_SB_type, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_SB_type, self).elaborate(platform)
# SB-type instruction format
m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25])
m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.ialign16.eq(0)
return m

26
insns/insn_UJ_type.py
View File

@ -1,26 +0,0 @@
from insn_general import *
class rvfi_insn_UJ_type(rvfi_insn_general):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_UJ_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
self.insn_rd = Signal(5)
self.insn_opcode = Signal(7)
self.misa_ok = Signal(1)
self.ialign16 = Signal(1)
def ports(self):
return super(rvfi_insn_UJ_type, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_UJ_type, self).elaborate(platform)
# UJ-type instruction format
m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.ialign16.eq(0)
return m

24
insns/insn_U_type.py
View File

@ -1,24 +0,0 @@
from insn_general import *
class rvfi_insn_U_type(rvfi_insn_general):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_U_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
self.insn_rd = Signal(5)
self.insn_opcode = Signal(7)
self.misa_ok = Signal(1)
def ports(self):
return super(rvfi_insn_U_type, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_U_type, self).elaborate(platform)
# U-type instruction format
m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
m.d.comb += self.misa_ok.eq(1)
return m

86
insns/insn_add.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_add(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# ADD instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_addi.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_addi(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# ADDI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata + insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0010011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_and.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_and(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# AND instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_andi.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_andi(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# ANDI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata & insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b0010011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

26
insns/insn_auipc.py
View File

@ -1,26 +0,0 @@
from insn_U_type import *
class rvfi_insn_auipc(rvfi_insn_U_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_auipc, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_auipc, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_auipc, self).elaborate(platform)
# AUIPC instruction
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~self.misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

30
insns/insn_beq.py
View File

@ -1,30 +0,0 @@
from insn_SB_type import *
class rvfi_insn_beq(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_beq, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_beq, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_beq, self).elaborate(platform)
# BEQ instruction
cond = Signal(1)
m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata)
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

30
insns/insn_bge.py
View File

@ -1,30 +0,0 @@
from insn_SB_type import *
class rvfi_insn_bge(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_bge, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_bge, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_bge, self).elaborate(platform)
# BGE instruction
cond = Signal(1)
m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata))
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

30
insns/insn_bgeu.py
View File

@ -1,30 +0,0 @@
from insn_SB_type import *
class rvfi_insn_bgeu(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_bgeu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_bgeu, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_bgeu, self).elaborate(platform)
# BGEU instruction
cond = Signal(1)
m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata)
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

30
insns/insn_blt.py
View File

@ -1,30 +0,0 @@
from insn_SB_type import *
class rvfi_insn_blt(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_blt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_blt, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_blt, self).elaborate(platform)
# BLT instruction
cond = Signal(1)
m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata))
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

30
insns/insn_bltu.py
View File

@ -1,30 +0,0 @@
from insn_SB_type import *
class rvfi_insn_bltu(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_bltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_bltu, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_bltu, self).elaborate(platform)
# BLTU instruction
cond = Signal(1)
m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata)
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

30
insns/insn_bne.py
View File

@ -1,30 +0,0 @@
from insn_SB_type import *
class rvfi_insn_bne(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_bne, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_bne, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_bne, self).elaborate(platform)
# BNE instruction
cond = Signal(1)
m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata)
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_div.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_div(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# DIV instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_divu.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_divu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# DIVU instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

50
insns/insn_general.py
View File

@ -1,50 +0,0 @@
from nmigen import *
class rvfi_insn_general(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
return m

28
insns/insn_jal.py
View File

@ -1,28 +0,0 @@
from insn_UJ_type import *
class rvfi_insn_jal(rvfi_insn_UJ_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_jal, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_jal, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_jal, self).elaborate(platform)
# JAL instruction
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

28
insns/insn_jalr.py
View File

@ -1,28 +0,0 @@
from insn_I_type import *
class rvfi_insn_jalr(rvfi_insn_I_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_jalr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_jalr, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_jalr, self).elaborate(platform)
# JALR instruction
next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111))
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_lb.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_lb(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# LB instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
result = Signal(8)
m.d.comb += result.eq(self.rvfi_mem_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b000) & (insn_opcode == 0b0000011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_lbu.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_lbu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# LBU instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
result = Signal(8)
m.d.comb += result.eq(self.rvfi_mem_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b100) & (insn_opcode == 0b0000011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_lh.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_lh(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# LH instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
result = Signal(16)
m.d.comb += result.eq(self.rvfi_mem_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b001) & (insn_opcode == 0b0000011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_lhu.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_lhu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# LHU instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
result = Signal(16)
m.d.comb += result.eq(self.rvfi_mem_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b101) & (insn_opcode == 0b0000011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

26
insns/insn_lui.py
View File

@ -1,26 +0,0 @@
from insn_U_type import *
class rvfi_insn_lui(rvfi_insn_U_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
super(rvfi_insn_lui, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
def ports(self):
return super(rvfi_insn_lui, self).ports()
def elaborate(self, platform):
m = super(rvfi_insn_lui, self).elaborate(platform)
# LUI instruction
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111))
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~self.misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_lw.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_lw(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# LW instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
result = Signal(32)
m.d.comb += result.eq(self.rvfi_mem_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b010) & (insn_opcode == 0b0000011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_mul.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_mul(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# MUL instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_mulh.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_mulh(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# MULH instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_mulhsu.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_mulhsu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# MULHSU instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0xea3969edecfbe137)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_mulhu.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_mulhu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# MULHU instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_or.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_or(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# OR instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_ori.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_ori(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# ORI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata | insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b0010011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_rem.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_rem(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# REM instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_remu.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_remu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# REMU instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1)
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_sb.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_sb(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# S-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SB instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0100011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1)
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
return m

84
insns/insn_sh.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_sh(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# S-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SH instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b0100011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1)
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
return m

88
insns/insn_sll.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_sll(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SLL instruction
shamt = Signal(6)
m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_slli.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_slli(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format (shift variation)
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct6 = Signal(7)
m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32])
insn_shamt = Signal(6)
m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SLLI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata << insn_shamt)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_slt.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_slt(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SLT instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_slti.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_slti(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SLTI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(insn_imm))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0010011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_sltiu.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_sltiu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SLTIU instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata < insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b011) & (insn_opcode == 0b0010011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_sltu.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_sltu(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format (shift variation)
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SLTU instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_sra.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_sra(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SRA instruction
shamt = Signal(6)
m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - shamt))) # https://stackoverflow.com/a/25207042
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_srai.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_srai(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format (shift variation)
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct6 = Signal(7)
m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32])
insn_shamt = Signal(6)
m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SRAI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq((self.rvfi_rs1_rdata >> insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - insn_shamt))) # https://stackoverflow.com/a/25207042
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b010000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

88
insns/insn_srl.py
View File

@ -1,88 +0,0 @@
from nmigen import *
class rvfi_insn_srl(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SRL instruction
shamt = Signal(6)
m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_srli.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_srli(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format (shift variation)
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct6 = Signal(7)
m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32])
insn_shamt = Signal(6)
m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SRLI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata >> insn_shamt)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

86
insns/insn_sub.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_sub(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SUB instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_sw.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_sw(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# S-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# SW instruction
addr = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0100011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_mem_addr.eq(addr)
m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1)
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
m.d.comb += self.spec_trap.eq(~misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
return m

86
insns/insn_xor.py
View File

@ -1,86 +0,0 @@
from nmigen import *
class rvfi_insn_xor(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# R-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_funct7 = Signal(7)
m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32])
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# XOR instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m

84
insns/insn_xori.py
View File

@ -1,84 +0,0 @@
from nmigen import *
class rvfi_insn_xori(Elaboratable):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self):
input_ports = [
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform):
m = Module()
# I-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32]))
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# XORI instruction
result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata ^ insn_imm)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b0010011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rd_addr.eq(insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m