M-Labs/riscv-formal-nmigen
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Fix minor bug in SRL instruction specification

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This commit is contained in:
Donald Sebastian Leung 2020-09-15 16:35:05 +08:00
parent c4daa89a88
commit e3b124f4eb
2 changed files with 2 additions and 2 deletions
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2
README.md
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@ -34,7 +34,7 @@ This should run in the order of a few hours.
- [ ] Instruction Checks (mostly passing)
- [x] JAL failing at line 202
- [ ] LB, LH, LW, LBU, LHU, SB, SH, SW: Parser error - invalid slice
- [ ] SRL failing at line 201
- [x] SRL failing at line 201
- [x] PC forward checks
- [x] PC backward checks
- [x] Register checks

2
rvfi/insns/insn_srl.py
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@ -6,7 +6,7 @@ SRL instruction
class InsnSrl(InsnRV32IRType):
def __init__(self, params):
super().__init__(params, 0b0000000, 0b100, 0b0110011)
super().__init__(params, 0b0000000, 0b101, 0b0110011)
def elaborate(self, platform):
m = super().elaborate(platform)