Add SLTU instruction
This commit is contained in:
parent
4d313ed54a
commit
cf9e1c741c
21
insns/insn_sltu.py
Normal file
21
insns/insn_sltu.py
Normal file
@ -0,0 +1,21 @@
|
||||
from insn_R import *
|
||||
|
||||
class rvfi_insn_sltu(rvfi_insn_R):
|
||||
def __init__(self):
|
||||
super(rvfi_insn_sltu, self).__init__()
|
||||
def ports(self):
|
||||
return super(rvfi_insn_sltu, self).ports()
|
||||
def elaborate(self, platform):
|
||||
m = super(rvfi_insn_sltu, self).elaborate(platform)
|
||||
|
||||
# SLTU instruction
|
||||
result = Signal(32)
|
||||
m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata)
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0110011))
|
||||
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||||
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
|
||||
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
|
||||
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
|
||||
|
||||
return m
|
Loading…
Reference in New Issue
Block a user