M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Refactor BGEU instruction

This commit is contained in:
Donald Sebastian Leung 2020-07-30 15:53:39 +08:00
parent 331cfda279
commit 9974db7e7b
1 changed files with 10 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
insns/insn_bgeu.py
View File

@ -1,88 +1,22 @@
from nmigen import * from insn_SB_type import *
class rvfi_insn_bgeu(Elaboratable): class rvfi_insn_bgeu(rvfi_insn_SB_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN super(rvfi_insn_bgeu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self): def ports(self):
input_ports = [ return super(rvfi_insn_bgeu, self).ports()
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform): def elaborate(self, platform):
m = Module() m = super(rvfi_insn_bgeu, self).elaborate(platform)
# SB-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
insn_rs2 = Signal(5)
m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25])
insn_rs1 = Signal(5)
m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20])
insn_funct3 = Signal(3)
m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
ialign16 = Signal(1)
m.d.comb += ialign16.eq(0)
# BGEU instruction # BGEU instruction
cond = Signal(1) cond = Signal(1)
m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata)
next_pc = Signal(self.RISCV_FORMAL_XLEN) next_pc = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + insn_imm, self.rvfi_pc_rdata + 4)) m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b1100011)) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1) m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2) m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~misa_ok) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rd_addr.eq(0)
m.d.comb += self.spec_rd_wdata.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m